FPGA Watchdog timer

[Altera_Forum]

Hello all, I'm working on a board with a Cyclone III LS. In the FPGA, we have implemented a watchdog functionality for the processor on the board. However, the customer now desires watchdog functionality for the FPGA itself. I figure I can pull nCONFIG low and then pull high to force (essentially) an FPGA reset using an external IC. But, has anyone heard of such a thing being done? I would think that FPGA's wouldn't "lock-up", and that this whole thing may introduce new issues, i.e. during power-up. 

 If anyone has any comments or direction, I'm all ears.  Thanks!

[Altera_Forum]

--- Quote Start ---   I figure I can pull nCONFIG low and then pull high to force (essentially) an FPGA reset using an external IC. But, has anyone heard of such a thing being done?   --- Quote End ---  Yes, I do this. You can consider this a function of the external programmer, i.e., if you want to clear the current configuration, you just pulse configN low.    --- Quote Start ---   I would think that FPGA's wouldn't "lock-up", and that this whole thing may introduce new issues, i.e. during power-up.   --- Quote End ---  FPGAs don't really lock-up, though there is the non-zero chance that an SRAM-based FPGA can have its configuration corrupted, eg., due to cosmic rays in a space-borne application (where you did not use a rad-hard FPGA).   In general your FPGA watchdog will be there to protect you from a critical state machine (with a coding error) that can get 'stuck'.   For example, consider the case of a processor with an FPGA on its external bus. When the processor does a read, the FPGA uses a handshake to accept the read, and then inserts wait-states until the read-data is valid. So what happens if the read-data is never valid ... the processor is locked up.  In this case though, the lockup would be cleared by an FPGA reset, rather than complete reconfiguration.  So you need to decide what kind of lock-up you are trying to protect against. I suspect you need a watchdog that will reset the FPGA, not force reconfiguration (or you could implement two watchdogs).  Cheers, Dave

[Altera_Forum]

Yes, our FPGA implemented watchdog also resets the FPGA itself when it issues the processor reset. 

 My thought was that if it's configuration load being corrupted (Their question was "What if it doesn't load right?"), but no matter how many times you reconfig, it won't un-corrupt that load.  I think their concern is that if the FPGA "stops working" they didn't know if there was a way to automatically wipe it clean and start fresh.

[Altera_Forum]

--- Quote Start ---   My thought was that if it's configuration load being corrupted (Their question was "What if it doesn't load right?"), but no matter how many times you reconfig, it won't un-corrupt that load.   --- Quote End ---  Correct - if the FPGA does not load due to a corrupt configuration, then a watchdog will not help.    --- Quote Start ---   I think their concern is that if the FPGA "stops working" they didn't know if there was a way to automatically wipe it clean and start fresh.  --- Quote End ---  Under what conditions are they expecting an FPGA to 'stop working'?  Cheers, Dave

[Altera_Forum]

Good question! 

 I'm not sure what they're thinking will happen.

[Altera_Forum]

--- Quote Start ---   I'm not sure what they're thinking will happen.  --- Quote End ---  Do let us know their response :)  Cheers, Dave