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Hi all,
I'd like to write a limiter: 1. Input/output are 16 bit signed number 2. If input is -32768 then output is limited by -32767, otherwise the output is just bypass of the input. I wrote a code as follow: ------------------- library ieee; use ieee.std_logic_1164.all; entity numLimiter16 is port( clk: in std_logic; data_in: in std_logic_vector(15 downto 0); data_out: out std_logic_vector(15 downto 0) ); end numLimiter16; architecture rtl of numLimiter16 is signal tmp : std_logic_vector(15 downto 0); begin process begin if (clk'event and clk='1') then data_out <= "1000_0000_0000_0001" when (tmp = "1000_0000_0000_0000") else tmp; end if; end process; tmp <= data_in; end rtl; -------------- When I compile the code I met the error message: Error (10500): VHDL syntax error at numLimiter16.vhd(21) near text "when"; expecting ";" Could you point out which one do I have to correct? Thanks!Link Copied
2 Replies
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Try this:
process(clk)
begin
if rising_edge(clk) then
if (data_in = X"8000") then
data_out <= X"8001";
else
data_out <= data_in;
end if;
end if;
end process;
Cheers, Dave
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Thanks Dave, works great!
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