a question about sourc e synchronous interface - Skew Approach

[Altera_Forum]

Hi Rysc, 

  I have a question about source synchronous interface. Could you pls help me? Question description is written into attached word file since a figure about source synchronous interface is contained.     looking forward to your help. thanks.    BR,   cxyfisher 

[Altera_Forum]

My first thought is that you're skipping over a critical part, which is the setup relationship and hold relationship. Without knowing that, the output delays make no sense. I assume when doing it my way, you've set up constraints to say the external latching clock is shifted 180 degrees(or inverted, same thing). This is how your waveforms are drawn, where they're latched on the falling edge. If you've dong that, the setup relationship is 3ns, so across the interface the data can be skewed +3 compared to the clock. Then when you state that external delay is 2ns, you're saying 2 of those ns are chewed up externally, and hence the FPGA can only skew its data by 1ns compared to the clock. On the hold analysis, the hold relationship is -3ns, i.e. the data can be skewed -3ns compared to the clock. Since -1ns of that is chewed up externally, then the FPGA can skew its data up to -2ns compared to the clock and still meet timing. In the end, the data can be skewed in the FPGA between -2 to +1ns compared to the clock going off chip. 

Now, the document you sent is very interesting. They do a setup multicycle of 0, which makes the setup relationship 0ns. They do a hold multicycle of -1, which makes the hold relationship also 0ns. (If this doesn't make sense, go to my TimeQuest User Guide on the wiki and look at the section on Multicycles). So in the end the setup relationship is 0ns and hold relationship is 0ns, so there can be absolutely no skew between the data and clock or it will fail timing. To be honest, I have never seen that done before and find it quite interesting. In fact, I kind of like it except for what it does to the external delays. With a setup relationship of 0ns, you have to say the -max external value is -1ns, i.e. externally there is a -1ns max skew so the FPGA now can have a +1ns skew and we'll still be at 0. The reverse is done for the hold analysis. The math is all correct, but you really can't conceptualize a -max value that is smaller than the -min value. It works because they're completely independent, i.e. the -max value is used in setup analysis and the -min value is used in hold analysis, and there is no check to see if it makes sense. Very interesting. Thanks for pointing that out. In the end its similar to the point I make about the Explicit versus Implicit Methods. For setup analysis, there are two variables used from your .sdc. One is the setup relationship(which comes from clock relationships and multicycles) and the other is the -max value. So a setup relationship of 3ns and -max value of 2ns leaves the FPGA with 3-2 = 1ns of skew to work with. But a setup relationship of 0ns and -max value of -1 will leave the FPGA with 0 - (-1) = 1ns of skew to work with. As you can see with two variables, there is more than one solution. In the end it's really trying to get to the one that makes the most sense.

[Altera_Forum]

sorry. I update word file so as to describe my question more explicitly. could you pls check attached word file again? thanks. 

 it seems that your methods are used to make sure data can't change within a window(setup+hold parameter of extern device) but those constraints in book are used to make sure data may change only within a window.  BR,  Fisher

[Altera_Forum]

I re-read the document but don't get what you're asking. Is it how the constraints from the book you reference work? I think I explained it above, at least as well as I know how.

[Altera_Forum]

Hi Rysc, 

 my question is:  what determine the parameters (2.0/-1.0) in "data may change only within a window "?  i know that 2.0 is determined by setup parameter of extern device and 1.0 is determined by hold parameter of extern device in "data can't change within a window". (of course it is based on skew approach).  set_output_delay -max 2.0 -clock CLKQ [get_ports DATAOUT]  set_output_delay -min -1.0 –clock CLKQ [get_ports DATAOUT]  but what determine the parameter (2.0/-1.0)in below constraint in "data can change only within a window"? how these two parameters are got by calculation? here assume external latch edge is the same edge as launch edge - source synchronous interface.  set_multicycle_path 0 -setup -to [get_ports DATAQ] set_multicycle_path -1 -hold -to [get_ports DATAQ]  set_output_delay -max -1.0 -clock CLK_STROBE [get_ports DATAQ]   set_output_delay -min +2.0 -clock CLK_STROBE [get_ports DATAQ]     Could you pls provide more details so as to help me to understand it? thanks  BR, cxyisher

[Altera_Forum]

Hi Rysc, 

 I have understood its calculation method and its physical meanness. Thank you very much.  BR,  cxyfisher

[Altera_Forum]

You figured it out but, but to add a little more, the "data can chane only in a window" comes from you, wich presumable comes from another device's datasheet. So you may be driving data to a device who's datasheet says, "The transmitter must send clock and data edge-aligned, wheter the data can change anywhere up to 1ns later than the clock to 2ns before". Or maybe it's a device that said it has a Tsu of 2ns and Th of 1ns. The way the waveform is drawn, it would be the same thing. (Of course no datasheets are ever that direct)  

That's one of the things that often gets lost, and I think the TI examples are very nice in that they list two transmitters, and yet the way to constrain them is very different.

[Altera_Forum]

Hi Rysc, 

 Yes, you are right. Thanks for your so patient help,  a timing figure is drawn to describe its calculation method and physical meanness.     again, thanks.  BR,  cxyfisher