inout Std_logic_vector Signal Test

[Altera_Forum]

Hi, 

 I am getting the following error by writting a testbench for Asynchrone SRAM and I have tried to solve this unsucessfully.Please any advice  error output:# ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024kx8.vhd(12): (vcom-1136) Unknown identifier "std_logic_vector".  vhdl code:  entity test_sram1024x8 is Line 12 PORT ( D : inout Std_logic_vector(7 downto 0)); end; architecture test of test_sram1024x8 is COMPONENT sram1024x8 port (A : in Std_logic_vector(19 downto 0); D : inout Std_logic_vector(7 downto 0); nCE : in std_logic; nCE2 : in std_logic; nWE : in std_logic; nOE : in Std_logic); END COMPONENT ; SIGNAL A : bit := '0'; SIGNAL nCE : bit := '1'; SIGNAL nCE2 : bit := '1'; SIGNAL nWE : bit := '1'; SIGNAL nOE : bit := '0'; begin dut : sram1024x8 PORT MAP ( A => A, D => D, nCE => nCE, nCE2 => nCE2, nWE => nWE, nOE => nOE ); --clock : PROCESS --begin --wait for 10 ns; clk <= not clk; --end PROCESS clock; stimulus : PROCESS begin --A <= '1'; wait for 5 ns; nCE <= '0'; wait for 5 ns; nCE2 <= '0'; wait for 5 ns; nOE <= '1'; wait for 12 ns; nWE <= '0'; wait; end PROCESS stimulus; end test;

[Altera_Forum]

you have probably forgotten to include thse lines: 

 library ieee; use ieee.std_logic_1164.all;

[Altera_Forum]

I also notice you're trying to map bits to std_logic - you cannot do that. You will have to type convert them. 

 Alternatively, dont use the bit type - use std_logic(_vector)

[Altera_Forum]

Thank you for your response 

I already use library ieee;use ieee.std_logic_1164.all; within my main component.  And I insert it again inside the current testbench and get the same error.  So which ccommand should I use to avoid inout std_logic_vector so that I could run my testbench?

[Altera_Forum]

--- Quote Start ---  I insert it again inside the current testbench and get the same error.  --- Quote End ---   Doesn't sound reasonable, please show the full text. Or it would be a case of mixed-up Modelsim configuration with missing IEEE libraries.

[Altera_Forum]

Ok here are my 2 files(vhdl Component + Testbench). 

Just take a look.  sram1024kx8.vhd  library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sram1024kx8 is port (A : in Std_logic_vector(19 downto 0); D : inout Std_logic_vector(7 downto 0); nCE : in std_logic; nCE2 : in std_logic; nWE : in std_logic; nOE : in Std_logic); end; architecture Behaviour of sram1024kx8 is subtype Byte is Std_logic_vector(7 downto 0); type Mem is array (0 to 1048576 ) of byte; signal Memory: Mem := (others => Byte'(others=>'U')); begin process(A, D, nCE, nCE2, nWE, nOE) begin D <= (others => 'Z'); if nCE='0' and nCE2='0' then if nOE = '0' then -- Read operation D <= Memory(To_Integer(unsigned(A))) after 10 ns; elsif nWE = '0' then -- Write operation Memory(To_Integer(unsigned(A))) <= D; end if; end if; end process; end;   and tsram1024kx8.vhd as testbench  library ieee; use ieee.std_logic_1164.all; entity test_sram1024x8 is PORT ( D : inout Std_logic_vector(7 downto 0)); end; architecture test of test_sram1024x8 is COMPONENT sram1024x8 port (A : in Std_logic_vector(19 downto 0); D : inout Std_logic_vector(7 downto 0); nCE : in std_logic; nCE2 : in std_logic; nWE : in std_logic; nOE : in Std_logic); END COMPONENT ; SIGNAL A : bit := '0'; SIGNAL nCE : bit := '1'; SIGNAL nCE2 : bit := '1'; SIGNAL nWE : bit := '1'; SIGNAL nOE : bit := '0'; begin dut : sram1024x8 PORT MAP ( A => A, D => D, nCE => nCE, nCE2 => nCE2, nWE => nWE, nOE => nOE ); --clock : PROCESS --begin --wait for 10 ns; clk <= not clk; --end PROCESS clock; stimulus : PROCESS begin --A <= '1'; wait for 5 ns; nCE <= '0'; wait for 5 ns; nCE2 <= '0'; wait for 5 ns; nOE <= '1'; wait for 12 ns; nWE <= '0'; wait; end PROCESS stimulus; end test;

[Altera_Forum]

compiles fine for me, except for the bit and std_logic incompatability I posted about earlier.

[Altera_Forum]

I don't really find out what is the Problem?

[Altera_Forum]

--- Quote Start ---  I don't really find out what is the Problem?  --- Quote End ---    If you're refering to the std_logic_vector not existing problem - then that is a setup problem on your system. The likelyhood is that you have somhow broken the std_logic_1164 package.  The other problem is a problem with your code because you have tried to assign a "bit" to a std_logic_vector. You cant do that because of VHDL's strong typing. You have two options to fix it.  1. Replace all bit(_vector) with std_logic_vector 2. use the to_std_ulogic/to_std_logic_vector conversion functions in the port map.

[Altera_Forum]

Now it compil without problem. 

 Just the error with inout std_logic_vector as follow: # ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024x8.vhd(38): Signal "a" is type std.standard.bit; expecting type ieee.std_logic_1164.std_logic_vector.  I will try your advice and see if I can move forward

[Altera_Forum]

Hi, 

 I fixed all errors but one is still there.  Please any advice for that?  persistance error # ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024x8.vhd(38): Array type for 'a' is not constrained.   code  library ieee; use ieee.std_logic_1164.all; entity test_sram1024x8 is PORT ( D : inout Std_logic_vector(7 downto 0)); end; architecture test of test_sram1024x8 is COMPONENT sram1024x8 port (A : in Std_logic_vector(19 downto 0); D : inout Std_logic_vector(7 downto 0); nCE : in std_logic; nCE2 : in std_logic; nWE : in std_logic; nOE : in Std_logic); END COMPONENT ; -------------------------------------- --signal A : Bit_vector(19 downto 0); --A <= ('0', others => '1'); -- 3 --DataBus <= DataBus(6 downto 0) & DataBus(7); -- 4 --DataBus <= "01110001"; --------------------------------------- --SIGNAL A : Std_bit_vector := "00000000000000000000"; -- Type T_Data is array (19 downto 0) of std_logic; SIGNAL A: Std_logic_vector:="00000000000000000000"; SIGNAL nCE : std_logic := '1'; SIGNAL nCE2 : std_logic := '1'; SIGNAL nWE : std_logic := '1'; SIGNAL nOE : std_logic := '0'; begin dut : sram1024x8 PORT MAP ( A => A, D => D, nCE => nCE, nCE2 => nCE2, nWE => nWE, nOE => nOE ); --clock : PROCESS --begin --wait for 10 ns; clk <= not clk; --end PROCESS clock; stimulus : PROCESS begin --A <= '1'; wait for 5 ns; nCE <= '0'; wait for 5 ns; nCE2 <= '0'; wait for 5 ns; nOE <= '1'; wait for 12 ns; nWE <= '0'; wait; end PROCESS stimulus; end test;

[Altera_Forum]

Well the problem is you have not constrained the signal A (please read your errors) 

 you need to give it a size. You can only constrain constants with an initialisation value.  signal a : std_logic_vector(19 downto 0) := (others => '0');

[Altera_Forum]

Hi guy, 

 I have finished with my SRAM Modeling and now my concern is to know how to integrated the timing requirement of my future Cypress Module?  Any Idea?

[Altera_Forum]

What exactly are you refering to? 

Do you want to simulate the design with a Cypress model? Or do you need to build a memory controller.  The previous code you posted is simply test code and not synthesisable. You will have to write a memory controller to get it to work in real hardware.

[Altera_Forum]

The external memory I intend to implement in my FPGA Project is from CYPRESS(8-Mbit (1024 K × 8) Static RAM) 

 Here is my controller :   --- Quote Start ---   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;   entity test_sram1024x8 is  PORT ( D : inout Std_logic_vector(7 downto 0)); end;  architecture test of test_sram1024x8 is  COMPONENT sram1024kx8  port (A : in Std_logic_vector(19 downto 0);  D : inout Std_logic_vector(7 downto 0);  nCE : in std_logic;  nCE2 : in std_logic;  nWE : in std_logic;  nOE : in Std_logic); END COMPONENT ;   SIGNAL A : std_logic_vector(19 downto 0) := (others => '0'); SIGNAL nCE : std_logic := '1'; SIGNAL nCE2 : std_logic := '1'; SIGNAL nWE : std_logic := '1'; SIGNAL nOE : std_logic := '1'; --SIGNAL D : std_logic_vector(7 downto 0):="00000000";  begin  dut : sram1024kx8 PORT MAP (  A => A(19 downto 0),  D => D(7 downto 0),  nCE => nCE,  nCE2 => nCE2,  nWE => nWE,  nOE => nOE );  stimulus : PROCESS  begin  --A <= '0000';  wait for 5 ns;   --A <= (others => '0');  --wait for 25 ns; -- Read Task  nCE <= '0';  nCE2 <= '0';  nWE <= '0';  --Write the value "i" at the address "i" for 10 clock cycles.  for i in 0 to 10 loop  A <= conv_std_logic_vector(i,20);  D <= conv_std_logic_vector(i,8);  wait for 10 ns;  end loop;    nOE<= '0';  --Read the RAM for addresses from 0 to 20.  for i in 0 to 10 loop  A <= conv_std_logic_vector(i,20);  wait for 10 ns;  end loop;  end PROCESS stimulus;  end test;   --- Quote End ---    Is that enough to fully control my Cypress SRAM? But there are also timing requirement on Cypress Datasheet?

[Altera_Forum]

Please sorry I send the false one here is the rigth controller: 

  entity sram1024kx8 is port (A : in Std_logic_vector(19 downto 0); D : inout Std_logic_vector(7 downto 0); nCE : in std_logic; nCE2 : in std_logic; nWE : in std_logic; nOE : in Std_logic); end; architecture Behaviour of sram1024kx8 is subtype Byte is Std_logic_vector(7 downto 0); type Mem is array (0 to 1048576 ) of byte; signal Memory: Mem := (others => Byte'(others=>'U')); begin process(A, D, nCE, nCE2, nWE, nOE) begin D <= (others => 'Z'); if nCE='0' and nCE2='0' then if nOE = '0' then -- Read operation D <= Memory(To_Integer(unsigned(A))) after 10 ns; elsif nWE = '0' then -- Write operation Memory(To_Integer(unsigned(A))) <= D; end if; end if; end process; end;

[Altera_Forum]

be aware that "after" keywords only work in simulation. They will be ignored for synthesis. 

 The code you currently had will create millions of latches (more than is avaiulable in any device) because of the way you are connecting to the memory. Memory in FPGAs has to be synchronous, so you will have to have a clock input and follow the templates for infering a RAM.  This new code is not a controller, it is a RAM.

[Altera_Forum]

Ok 

 You are rigth but what I am wondering is the fact that I have a reference Design from Arrow interfacing with an external memory. Take a look below:  There is no top level vhdl file specified (top_level_hdl_file "" ).  It means they just wrote a _hw.tcl as interface to the external SRAM.  What that means ? such a connection without specified SRAM Controller?    package require -exact sopc 9.1# | # +----------------------------------- # +-----------------------------------# | module ext_ram_16# | set_module_property DESCRIPTION "Interface to an IS61VPS102418A device" set_module_property NAME IS61VPS102418A set_module_property VERSION 1.0.0 set_module_property INTERNAL false set_module_property GROUP "CycloneIV Starterkit Components" set_module_property AUTHOR "Arrow Electronics" set_module_property DISPLAY_NAME "IS61VPS102418A SRAM" set_module_property TOP_LEVEL_HDL_FILE "" set_module_property INSTANTIATE_IN_SYSTEM_MODULE false set_module_property EDITABLE true set_module_property ANALYZE_HDL TRUE# | # +-----------------------------------

[Altera_Forum]

the SRAM controller could be part of their IP catalogue,, and the TCl connects it to the SRAM. TCL cannot be used directly to create an SRAM controller. It could generate the VHDL/verilog though. 

 Are you sure its not a verilog file?

[Altera_Forum]

I think you are rigth. Can you give me some advice how an asynchrone SRAM Controller looks like ? or what I should pay attention ?

[Altera_Forum]

you wouldnt have an asynchronous SRAM controller because the SRAM is already synchronous.