Programmable Devices
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Driving AdressData on the same Bus

Altera_Forum
Honored Contributor II
‎11-09-2011 08:25 AM
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Hi, 

 

Please can somebody give me any advice how the VHDL Code for driving the 

A0-A7=D0-D7 with the Latch Register could looks like. 

 

I have been trying without success to solve it. 

 

I would appreciate any response 

 

Regards,
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Altera_Forum
Honored Contributor II
‎11-09-2011 08:41 AM
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You are talking about the FPGA part to drive the multiplexed bus? Start with sketching a timing diagram.

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Altera_Forum
Honored Contributor II
‎11-09-2011 09:34 AM
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Ok, but what do you means by sketching the timing Diagram? 

 

I have never done such a thing before. 

My entire project looks like the attached file. So the Databus should be used simultaneously by SRAM-I/O and LED. 

Please I would appreciate your advice. 

 

Regards,
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