Are outputs of PLL related all the time?

[Altera_Forum]

Hi, 

 Currently, i am timing constraining my FPGA design. I would like to know are the outputs of PLL related with each other (sync) all the time?   1)What if the output frequency is multiple of the input frequency ? 2)What if the output frequency is NOT multiple of the input frequency ? 3)What if the output frequency is phase shifted of the input frequency ? 4)What if the output frequency is phase shifted and multiple/non-multiple of the input frequency ? (depending on question 3, if answer to question 3 is NOT, then this is probably NOT as well...i guess)   Anyone who knows, please give me a quick answer:). Thank you!  Regards, Michael

[Altera_Forum]

Relation of PLL outputs to input and to each other is provided by resetting all involved dividers to a defined initial value. As long as the PLL doesn't loose lock, the relation will be kept during operation. 

 Keeping a fixed phase relation between outputs doesn't depend on output:input frequency ratio. Obviously it depends on the exact ratio of output frequencies.

[Altera_Forum]

Indeed as long as PLL stays in lock then you shouldn't worry.  

I don't see that jitter will vary practically with your conditions for a given PLL but the meaning of "locked" is arbitrary and depends on how much jitter is accepted as "locked"  The loop is analogue and is based on phase error detection between internal osc frequency Fosc,and generated frequency Fout, followed by damping through loop filter then applying erorr in reverse on oscillator.  The error will never become zero but will "oscillate" up and down with possible variation over time/temperature. Then jitter = amplitude of error oscillation.  Jitter may not be same at all cases of chosen frequency values but can be forced for better by modifying loop filter.

[Altera_Forum]

no.. thats not what i want to know. 

All i want to know is that, how should i group the output of PLL during the timing contraint process.  For example:  set_clock_groups -asynchronous  -group {adc_clk  adcpll_output[0]  adcpll_output[1]} -group {sys_clk  syspll_output[0]  adcpll_output[2]}   something like these... so my original question was, how should i group these pll clock if; 1)What if the output frequency is multiple of the input frequency ? would it be in different group or same group? 2)What if the output frequency is NOT multiple of the input frequency ? would it be in different group or same group? 3)What if the output frequency is phase shifted of the input frequency ? would it be in different group or same group? 4)What if the output frequency is phase shifted and multiple/non-multiple of the input frequency ? would it be in different group or same group?  Sorry for the confusion.  Regards, Michael

[Altera_Forum]

Basically you want to know how to determine if two clocks are 

related or not so that you decide if their domain needs bridge or not.  The rule of thumb is this: if in doubt treat them as unrelated.  If two clocks are always related to each other in a fixed predictable pattern then you may manage without a bridge.  So you can draw out your waveforms and see effect of frequency and phase.

[Altera_Forum]

Thanks for your reply. so now i know "unrelate" a related clock will not harm. 

 Could you also answer my previous 4 questions? it will be used for my reference, as to whether to relate or not to relate.  To my understanding, related clocks basically means "In Sync", so output of pll producing the multiple of input frequency are still consider "In Sync", but if it has been phase shifted, means they are "NOT in Sync". Am i right?

[Altera_Forum]

--- Quote Start ---   1)What if the output frequency is multiple of the input frequency ?   --- Quote End ---  the slow clock will always align edge with fast clock(in sync) as long as they are phase aligned    --- Quote Start ---   2)What if the output frequency is NOT multiple of the input frequency    --- Quote End ---  slow clock cannot align at every edge (Out of sync)    --- Quote Start ---   3)What if the output frequency is phase shifted of the input frequency    --- Quote End ---  never edge aligned but fixed relation(related but not in sync)    --- Quote Start ---   4)What if the output frequency is phase shifted and multiple/non-multiple of the input frequency    --- Quote End ---  never edge aligned(related but not in sync) / neither