mapping a port to several signals

[Altera_Forum]

Hi all! 

 I have got an issue, I don't really know if it's a bug from ModelSi or an error from my code. Maybe soeone will be able to tell me...  A/° I am using:    --- Quote Start ---  ModelSim DE 6.6a Revision: 2010.03 Date: Mar 19 2010  --- Quote End ---      B/° This code works:  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is end entity test; architecture behavioural of test is component foo port ( s : out std_logic_vector(31 downto 0) ); end component foo; constant K : natural range 1 to 31 := 15; signal msb : std_logic_vector(31 downto K); signal lsb : std_logic_vector((K - 1) downto 0); begin foo_inst : foo port map ( s(31 downto K) => msb, s((K - 1) downto 0) => lsb ); end architecture behavioural;    --- Quote Start ---  ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd # Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Compiling entity test # -- Compiling architecture behavioural of test ModelSim>   --- Quote End ---      C/° I tried to replace the constant K with e generic that I can set when starting the simulation, but it does not work  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is generic ( K : natural range 1 to 31 := 15 ); end entity test; architecture behavioural of test is component foo port ( s : out std_logic_vector(31 downto 0) ); end component foo; signal msb : std_logic_vector(31 downto K); signal lsb : std_logic_vector((K - 1) downto 0); begin foo_inst : foo port map ( s(31 downto K) => msb, s((K - 1) downto 0) => lsb ); end architecture behavioural;    --- Quote Start ---  ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd # Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Compiling entity test # -- Compiling architecture behavioural of test # ** Error: /home/reinauld/Bureau/test.vhd(29): (vcom-1024) Individually associated formal "s" must be identified with a locally static name. # ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1024) Individually associated formal "s" must be identified with a locally static name. # ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1048) Non-locally static choice (association# 2, choice# 1) is allowed only if it is the only choice of the only association. # ** Error: /home/reinauld/Bureau/test.vhd(33): VHDL Compiler exiting # /opt/modelsim_de/modelsim_dlx/linuxpe/vcom failed. ModelSim>   --- Quote End ---      Can anyone comment this? Maybe suggest another way to achieve what I try to do?  The point is to map output of a signal driver (that reads stimuli from a file) to several stimuli signals.    Thanks,  Julien

[Altera_Forum]

The compiler needs to settle what to connect to what i.e. k must be a constant per build

[Altera_Forum]

The VHDL standard doesn't provide the option to connect variable bits or slices of port signal individually. But it's easy to connect s as a whole to a wire signal and individual slices of it as intended.

[Altera_Forum]

use: 

generic( k : integer := 15 );

[Altera_Forum]

@kaz:  

--- Quote Start ---  The compiler needs to settle what to connect to what i.e. k must be a constant per build  --- Quote End ---   a generic is set at compilation time, so it behaves like a constant. It's not a signal that can vary in time...    @FvM:   --- Quote Start ---  The VHDL standard doesn't provide the option to connect variable bits or slices of port signal individually  --- Quote End ---   yes it does (one proof is that 1st version of code compiles)   --- Quote Start ---  But it's easy to connect s as a whole to a wire signal and individual slices of it as intended.  --- Quote End ---   True :)    @kaz   --- Quote Start ---  use: generic( k : integer := 15 );  --- Quote End ---   This does not change anything...

[Altera_Forum]

Your test entity has only generic and your msb/lsb are undriven internal signals and this is not standard code.  

A generic constant should be acceptable by any sensible compiler.

[Altera_Forum]

--- Quote Start ---  @kaz: a generic is set at compilation time, so it behaves like a constant. It's not a signal that can vary in time...   --- Quote End ---    Almost, but not quite.  A constant is a known value when you compile the code. A generic may not have a default value when you compile the code, so it is only fixed when you isntantiate the entity, so therefore it is not static, and hence the error when you compile the code.    --- Quote Start ---   @FvM: yes it does (one proof is that 1st version of code compiles) True :)   --- Quote End ---    See the above comment     --- Quote Start ---   @kaz This does not change anything...  --- Quote End ---    yes it does, because generics are not static.

[Altera_Forum]

@kaz  

--- Quote Start ---  Your test entity has only generic and your msb/lsb are undriven internal signals and this is not standard code.  --- Quote End ---   I disagree :) - msb and lsb signals are driven since they are mapped to 'out' ports of an instanciated component. - Entities without ports but only generics are pretty common for testbenches, there is nothing exotic here...    @Tricky   --- Quote Start ---   Quote: @kaz This does not change anything...  yes it does, because generics are not static.  --- Quote End ---   Sorry I was not clear. I meant I tried and I get the same error :)    @Tricky   --- Quote Start ---  Almost, but not quite.  A constant is a known value when you compile the code. A generic may not have a default value when you compile the code, so it is only fixed when you isntantiate the entity, so therefore it is not static, and hence the error when you compile the code.  --- Quote End ---   I see: functionally, I (designer) know that it must work (because of the way I caculate indexes and the range I authorized for the generic) but the compiler itself can not do this kind of thinking. So it can not perform sanity check on the way I slice the port among several signals at compilation time since it does not know the values that the generic has... That's why I get the error.

[Altera_Forum]

constant generics are accepted by quartus and modelsim. 

If you get error then you got something else wrong. Your msb/lsb yes are driven by output s (possibly so from inside your component that has no inputs and it could be generating output only...??) however your msb/lsb is driving nothing and your top entity is not valid without ports.

[Altera_Forum]

--- Quote Start ---  constant generics are accepted by quartus and modelsim. If you get error then you got something else wrong. Your msb/lsb yes are driven by output s (possibly so from inside your component that has no inputs and it could be generating output only...??) however your msb/lsb is driving nothing and your top entity is not valid without ports.  --- Quote End ---    It is perfectly valid as a testbench (as this code would be) so you wouldnt compile it in quartus.  There is not such thing as a constant generic. Generics are only constant at instantiation. You can still override top level generics from the command line of modelsim when you run something like:  vsim -Gwidth=10  so the generic is not set until you actually run vsim. This is why the generic is not static or constant and hence why you get the error that the OP had. slices in port maps MUST be static.

[Altera_Forum]

Generic is meant for component and should be constant at instantiation then. But above code has no generic at component level but at top. I don't see this code has any meaning whatsoever to test compilers.

[Altera_Forum]

Still, ModelSim is not consistent 

   Slices with indexes that are not static: - are not allowed in port mapping - BUT are allowed in continuous affectations (in this case, if slices are wrong, the code compiles but the simulation crashes with an error message during load)    The following examples illustrate this: they are perfectly identical from a functional point of view, but one compiles and the other does not.  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is generic ( K : natural range 1 to 31 := 15 ); end entity test; architecture behavioural of test is component foo port ( s : out std_logic_vector(31 downto 0) ); end component foo; signal msb : std_logic_vector(31 downto K); signal lsb : std_logic_vector((K - 1) downto 0); begin foo_inst : foo port map ( s(31 downto K) => msb, s((K - 1) downto 0) => lsb ); end architecture behavioural;    --- Quote Start ---  ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd # Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Compiling entity test # -- Compiling architecture behavioural of test # ** Error: /home/reinauld/Bureau/test.vhd(29): (vcom-1024) Individually associated formal "s" must be identified with a locally static name. # ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1024) Individually associated formal "s" must be identified with a locally static name. # ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1048) Non-locally static choice (association# 2, choice# 1) is allowed only if it is the only choice of the only association. # ** Error: /home/reinauld/Bureau/test.vhd(33): VHDL Compiler exiting ModelSim>   --- Quote End ---      library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is generic ( K : natural range 1 to 31 := 15 ); end entity test; architecture behavioural of test is component foo port ( s : out std_logic_vector(31 downto 0) ); end component foo; signal sig : std_logic_vector(31 downto 0); signal msb : std_logic_vector(31 downto K); signal lsb : std_logic_vector((K - 1) downto 0); begin foo_inst : foo port map ( s => sig ); msb <= sig(31 downto K); lsb <= sig((K - 1) downto 0); end architecture behavioural;    --- Quote Start ---  ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd # Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Compiling entity test # -- Compiling architecture behavioural of test ModelSim>   --- Quote End ---      Is there a reason?

[Altera_Forum]

@kaz  

 The code I proposed is for illustration only, it has no purpose.    However you can imagine a testbench that generates stimuli from a file, instanciate a DUT, and checks outputs of the DUT in a process, reporting errors whenever they occur.  This testbench would be an entity with no port, but with a generic for the stimuli file name for instance (in order to be able to run various scenarios without recompiling the testbench each time) --> just as in my example code.  Also, it would instanciate a module as stimuli driver. This module would read the stimuli file and drive an 'out' signal accordingly. So basically this module would have only an 'out' port --> just as in my example code. (In that case, the driver would have the same generic as the testbench, and the generic would be propagated from the bench to the driver. But since this has nothing to do with my concern, so it was not necessary to my example code)

[Altera_Forum]

--- Quote Start ---   Is there a reason?  --- Quote End ---    yes. It will be part of the VHDL LRM that port maps have to be static but signal assignments dont need to be.

[Altera_Forum]

And do you know the reason for that?

[Altera_Forum]

Because rules are rules!! Dont question the LRM. ;) 

 from the '93 LRM, section 1.1.1.2 Ports, line 94: "The actual, if a port or signal, must be denoted by a static name. The actual, if an expression, must be a globally static expression"

[Altera_Forum]

Ok then ;)