LPMs and ASICs

[Altera_Forum]

I've been working on a digital signal processing design for a Cyclone IV design and have been using LPM-based arithmetic blocks in order to get the clock speed up. 

 My client just asked me if an ASIC vendor would be able to take the finished design and use it as part of an ASIC. This wouldn't be an Altera hardcopy device.  I don't have direct experience with ASICs. Does anyone have any experience with ASIC conversion and whether I'd have to write RTL from scratch to replace the LPM's?

[Altera_Forum]

Major ASIC EDA tools (like Synopsys) also provide various kinds of megafunction/IP cores in their library. First you need to know the target fab process of your ASIC client, then check if with this particular process, your megafunction/IP is supported in the library of your synthesis tool. 

 (Basic arithmetic blocks, like adder and multiplier, usually can be directly synthesized with ASIC tools.)