Nios II basic questions

[Altera_Forum]

Hi all, 

I've done some VHDL coding but I never used Nios II. I need to design a board so that on one side it will connect to a PC (via ethernet or USB) and on the other side it will function as a standard FPGA. I understand that Nios II is a good solution for that (correct me if I'm wrong).  My question is regarding the development tools and the coding process: In my project the SW guys are supposed to write the PC interface and I'm supposed to do the FPGA coding, while the data from the PC should be forwarded to the FPGA after some processing. Is it possible to write the 2 codes independently as if we were using separate uC and FPGA? Or do we have to write all the code in the same project/environment? What is the integration process between the C and VHDL codes?  Please explain how exactly this works.  Thanks in advance

[Altera_Forum]

--- Quote Start ---  Is it possible to write the 2 codes independently  --- Quote End ---   Yes, people can work separately but it's obvious that if they use NIOSII, they need also to be working on QuartusII, and NIOSII EDS. You do not necessarily need to connect the NIOSII to the rest of the FPGA. You can also use multi NIOSII on the same FPGA, every one for a different task. for Ethernet case with NIOSII, you need Nichestack wich is with License. The link between HDL and C is the .sopcinfo file generated by SOPC or QSys. They give you the HDL file to add to your top level as well as the .sopcinfo that will generate a BSP file system to compile your code.

[Altera_Forum]

Hi WASS, 

Thanks for the quick response.  Just to make sure that I understand you correctly, you mean that the SW guys will write the C code in NIOSII EDS and I will write the VHDL code in Quartus. The C code will be compiled into a .sopcinfo file which can be added to my VHDL project as a VHDL entity and then the whole project will be referred to as a standard VHDL project and will be burned to the FPGA using the standard tools (i.e. ByteBlasterII). Am I correct?  Thanks

[Altera_Forum]

No, not exactly 

you have a high level synthesis tool called SOPC that you run from within QuartusII SOPC generates SOPCStructure.vhdl that you include in your top level and synthesize with QuartusII to get the .sof or .pof to configure your FPGA. your FPGA can run with the NIOSII beeing inside but Idle, now to make it run the independent process is to: Start the NIOSII IDE tool, create a project based on the intermediate file .sopcinfo generated by SOPC, write all your C code, compile it to get a .elf file. that is like an exe of NIOSII. once the FPGA is running with the corresponding .sof file, you can upload the .elf to the memory that the NIOSII will run from. I'm not going into detail because the purpose is only to give you a general idea, if you keep this solution for sure, then I won't do better than the abundant doc and tutorials around NIOSII.