Friends,in my design i am using a 50Mhz clock from fpga. but i need a clock of 1 khZ or less. i want to know about how to use pll in fpga my device name :EP2S60F672C3 Thanks in advance
1 kHz is too low a frequency for a pll. You need to use counters to generate a 1kHz signal. If you need it as a clock inside your system, you can use the generated 1kHz signal as a clock enable.
