about Tri-State Logic gate

[Altera_Forum]

i want to make a Tri-State Logic gate,but the putout is always high impedance .why 

here's my code&#65307; library ieee; use ieee.std_logic_1164.all; entity e is port( datain:in std_logic_vector(7 downto 0); enable:in std_logic; dataout:out std_logic_vector(7 downto 0) ); end e; architecture b of e is begin process(enable,datain) begin if (enable='0') then dataout<="ZZZZZZZZ"; else dataout<=datain; end if; end process; end b;

[Altera_Forum]

dataout needs to be an inout to have a tristate

[Altera_Forum]

but is the problem in simulation or on hardware?

[Altera_Forum]

in simulation.but it's so strange.today i try again.when enable is 1,dataout is same as datain.but when enable is 0,dataout is always 0.so my question is changed.dose 0 stand for high impedance in quartus ii?

[Altera_Forum]

anyone?help.

[Altera_Forum]

did you make dataout an inout port? it wont work as just an out port. 

And is this an RTL simulation or post place and route?

[Altera_Forum]

thank you.when i change dataout to inout,it works well.at first,i thought "inout" means "buffer",because i never learned inout.

[Altera_Forum]

inout is needed for tri-state buffer on real hardware. 

a "buffer" type is an output that can be read internally (it is NOT tri-stated). It is quite rarely used, as most coding guidelines recommend you use internal signals instead.

[Altera_Forum]

can you tell me why

[Altera_Forum]

you cannot read an out port, so there is no need to tri-state it. Because of that your logic got converted to a mux. 

 I am assuming you did a post compilation simulation, because you would have seen no problems with an RTL simulation (and then the differences between hardware and simulation would have caused you problems).

[Altera_Forum]

thank you very much