DDR2 HPC 11.1 Saga

[Altera_Forum]

I don't know whether to laugh or cry ... 

I instantiated an DDR2 HPC II controller with AltMempPHY for Cyclone IV E: EP4CE30F17C8N with MT4732M16HR-25E (16 bit device) and it uses 6175 lcs! And it only has to run 125MHz. But even at 200 MHz (which is the maximum DDR2 frequency for Cyclone speed grade C6) this is a humongous over-usage of LCs. The previous version 11.0sp1 was already 2500+ LCs. What happened? I just removed 11.0sp1 from my system, but it looks like I will have to get that back :(

[Altera_Forum]

wow. i'll probably look into this one 

 have you filed an SR?

[Altera_Forum]

--- Quote Start ---  wow. i'll probably look into this one  have you filed an SR?  --- Quote End ---    No, I haven't filed an SR. I have seen the DDR2 controller grow over the years, I just assume this is the latest 'release'. Of course the designers at Altera target Stratix V designs where the performance is paramount, and where you do not have to care about a 'few' LCs. But our projects are quite cost sensitive, the customer wants a 50% max usage for future enhancements and then we start throwing them out by the bucket. Surprisingly the controller is not encrypted ...

[Altera_Forum]

--- Quote Start ---  No, I haven't filed an SR. I have seen the DDR2 controller grow over the years, I just assume this is the latest 'release'. Of course the designers at Altera target Stratix V designs where the performance is paramount, and where you do not have to care about a 'few' LCs. But our projects are quite cost sensitive, the customer wants a 50% max usage for future enhancements and then we start throwing them out by the bucket. Surprisingly the controller is not encrypted ...  --- Quote End ---    Afaik the controller itself is not encrypted, but the control logic is encrypted.

[Altera_Forum]

--- Quote Start ---  Afaik the controller itself is not encrypted, but the control logic is encrypted.  --- Quote End ---   I re-checked and I could open every file shown in the Navigator panel, hence my surprise ... Previously the controller was encrypted, and the AltMemPHY (or the Legacy PHY) was not. --- 22-11-2011 --- I did put in an SR. --- With hindsight I decided to take a look at the doc for 11.1 and this is what I found for DDR2 in Cyclone III :  Memory width Logic Registers Logic cells M9K blocks Memory Bits 16 2,915 5,351 9 9,392 So I will get no pie ...

[Altera_Forum]

Things get even worse: we regenerated the QSys project on another machine (Linux), and after enabling the CSR memory slave the LC usage soared to 9300 LCs.

[Altera_Forum]

Maybe You can share the project (if it's not a commercial secret ofcourse), so someone on the forum could also compile and test the results? 

 I am also planning a Cyclone III EP3C40 + DDR2 system, but if it eats so much logic, it doesn't make sense then...

[Altera_Forum]

--- Quote Start ---  Maybe You can share the project (if it's not a commercial secret of course), so someone on the forum could also compile and test the results?  I am also planning a Cyclone III EP3C40 + DDR2 system, but if it eats so much logic, it doesn't make sense then...  --- Quote End ---   It is a run of the mill Qsys thing: ddr2 - a single MT47H32M16HR-25E internal static memory 4kB TSE SGDMA Rx, Tx Nios II/s SpiMaster (connecting a small external supervisor micro-controller which also accesses all MM slave ports) Pio 4 pc. to test the FPGA IO  all this in an EP4CE30F23C8N, consuming 22033 LCs of the 28k+ available ...

[Altera_Forum]

Are You sure You have not enabled faster fmax settings, like optimization: speed, register duplication, etc?

[Altera_Forum]

--- Quote Start ---  Are You sure You have not enabled faster fmax settings, like optimization: speed, register duplication, etc?  --- Quote End ---    NO, standard: balanced, timing-driven synthesis, auto-fit

[Altera_Forum]

Eh.. then I am out of ideas. Altera engineers should check this out. I've also planned a design with Cyclone III and DDR2, but now will probably keep with DDR.

[Altera_Forum]

Open a service request at www.altera.com

[Altera_Forum]

--- Quote Start ---  Open a service request at www.altera.com  --- Quote End ---    I did file an SR and this was the reply:   --- Quote Start ---  Hi Josy,  This is because there are some changes and modification in IP for QII V11.1 which cause the LC usage to increase. This is out of my control as this QII V11.1 is designed by IP engineering team. Hope you understand this. Thanks again for using my support.  Regards, Allen  --- Quote End ---    Things are definitely out of control :o

[Altera_Forum]

I guess you have to create an SR again and ask them to send it to the right person this time... :blink:

[Altera_Forum]

Are there any news about this problem?

[Altera_Forum]

--- Quote Start ---  Are there any news about this problem?  --- Quote End ---    Not yet, as I only insisted today that they give me a better answer. Anyway we have decided to live with it for the development phase of our project, and see what develops.

[Altera_Forum]

Did You install the update regarding DCFIFO?

[Altera_Forum]

--- Quote Start ---  Did You install the update regarding DCFIFO?  --- Quote End ---    Of course I did, but that has nothing or whatsoever to do with the LC usage ...

[Altera_Forum]

Eh.. unlucky :/ I wonder if anyone also experienced this issue?