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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error: WYSIWYG primitive "mac_mult1" has DATAB port with specified width of 12, but o

Altera_Forum
Honored Contributor II
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Hello, 

 

 

I came across the following error message: 

Error: WYSIWYG primitive "mac_mult1" has DATAB port with specified width of 12, but only 0 bits are connected 

 

Double clicking leads me one file in db folder and I could not locate the actual location. 

 

 

I found similar thread here and the thread says there is possibility of typo of names in the design (I am using connection by names). However, I didn't modify the file over some time and a few minutes before it compiled successfully. 

 

My design is huge and finding each element is a headache. Is there anyway to locate the actual part in the design file? 

 

Thanks for any help or suggestion!
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Altera_Forum
Honored Contributor II
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what are you designing in? graphical design? if your file is huge then thats your problem, you should have broken it down more maybe 

 

try deleting the "db" folder.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

what are you designing in? graphical design? if your file is huge then thats your problem, you should have broken it down more maybe 

 

try deleting the "db" folder. 

--- Quote End ---  

 

 

 

Thank you, Tricky. 

Yes, I am using schematic method.  

I deleted the "db" folder but it didn't change anything. I noticed that in the project navigator, there is a tdf file pointing out the location in the db folder. Do you think it is good to delete the tdf file from the project navigator? I am wondering the tdf file is automatically included when Quartus is doing compilation.  

 

What do you mean by "broken down"? You meant hierarchical design? If you meant it, I already did it that way; Clicking some schematic blocks, it leads inside the block. And inside the block, there are other sub-blocks, and I can go inside by clicking the blocks again until I meet unit elements (primitives or mega-functions) which Altera provided for design. 

 

 

Thanks for the comments!
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Altera_Forum
Honored Contributor II
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basically, it sounds like something is unconnected somewhere. I wouldnt delete a file if its in the project navigator as you probably need it. The DB folder is just temporary files. 

 

Unfortunatly because you've used schematics simulation is not really an option.
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Altera_Forum
Honored Contributor II
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Resolved by RTL viewer. It displayed disconnected ports!

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