Help defining Global Clock Signals

[Altera_Forum]

I am building a DSP structure for a Cyclone III and I am using Quartus II and Verilog to design it. I am trying to be as modular as possible. The design is also as synchronous as it can be. This DSP structure is seen by the NIOS II as a peripheral module. 

 The final design follows a hierarchical modular structure: The main module (as seen by the NIOS2) contains several more modules interconnected, each of which may also contain more modules. So far, I think that is a very standard type of design.   I am testing each of the basic modules independently in my hardware platform. For the tests I use the NIOS processor to interface (read/write) with the module. I verify the behavior through the NIOS console. So far the modules are working fine independently.   My problem occurs when I try test the system with more than one module in a hierarchy larger than 1. It simply does not work. I believe I have a problem with the clock signals.    I understand that it is recommended to declare the main clock signals global so that the router gives preference to these to ensure the proper execution of the system.    I also know that there is a GLOBAL PRIMITIVE both in verilog and in Quartus. I just do not know how to use it. Should I declare the global signals in each module? Or will it suffice if I declare the globals at the top of the hierarchy in my design (this would assume that any wire or port connected to a global wire becomes global too)   I look forward to your comments

[Altera_Forum]

Quartus puts clocks onto globals very quickly. Only under extreme conditions(like more clocks than globals or perhaps a clock with a small fanout, such as less than 10) might it not do this. The most important thing is that you have timing constraints in the .sdc describing the clocks. As long as you do that, then however the design is routed, it will be analyzed. Heck, if all the clocks were using local routing and it passed timing, then there shouldn't be any problems.  

Do you have gated clocks in your design? Besides that, I doubt clocks are the issue. (And if you do have gated clocks, the problem is not whether or not they're on globals, but that they're constrained correctly)