"LPM_MULT" Modelsim simulation problem

Altera_Forum · ‎11-26-2011

I defined a LPM_MULT in my vhdl design as follows:

--##################################

COMPONENT LPM_MULT

GENERIC (

LPM_WIDTHA : NATURAL;

LPM_WIDTHB : NATURAL;

LPM_WIDTHS : NATURAL := 1;

LPM_WIDTHP : NATURAL;

MAXIMIZE_SPEED : NATURAL := 8;

LPM_REPRESENTATION : STRING := "UNSIGNED";

DEDICATED_MULTIPLIER_CIRCUITRY : STRING := "YES";

INPUT_B_IS_CONSTANT : STRING := "NO";

LPM_PIPELINE : NATURAL := 0;

LPM_TYPE : STRING := "L_MULT";

LPM_HINT : STRING := "UNUSED");

PORT (

DATAA : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);

DATAB : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);

ACLR : IN STD_LOGIC := '0';

CLOCK : IN STD_LOGIC := '0';

CLKEN : IN STD_LOGIC := '1';

SUM : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS=> '0');

RESULT : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0)

);

END COMPONENT;

--###############################################

then i mapped the component as follows:

mult_icos : LPM_MULT

GENERIC MAP(

LPM_WIDTHA => 6,

LPM_WIDTHB => 8,

LPM_WIDTHS => 1,

LPM_WIDTHP => 8+6,

MAXIMIZE_SPEED => 9,

LPM_REPRESENTATION => "SIGNED",

DEDICATED_MULTIPLIER_CIRCUITRY => "YES",

INPUT_B_IS_CONSTANT => "YES",

LPM_PIPELINE => 1,

LPM_TYPE => "L_MULT",

LPM_HINT => "UNUSED")

PORT MAP(

DATAA => Iin_reg,

DATAB => cos_in_reg,

ACLR => reset,

CLOCK => clock,

CLKEN => resetn,

SUM => (OTHERS=> '0'),

RESULT => icos

);

I writed a testbench and simulated the vhdl code in modelsim. I added the lpm, altera, altera_mf and sgate libraries to modelsim, and simulated the project, then prompted the warning: component instance "mult_icos: lpm_mult " is not bound. I ignored the warning and started simulation. I analyzed the simulation result when the simulation proess was over, and found that the lpm_mult didn't work. I don't know why the lpm_mult doesn't work. Do I miss any libraries or other anyhow questions? Can somebody help me? Thanks a lot.

Altera_Forum · ‎11-26-2011

An easy way to get a mult is just use icos <= i * cos; and you get same result except that you may not have internal pipeline > 0.

Alternatively, use megawizard to do the job for you.

Your mult has some strange ports to me. You may also check that you are using the correct version of lpm library

Altera_Forum · ‎11-26-2011

I want to use the dedicated multiplier but reluctant to use ip core, which generates too much files, so writed the vhdl code. I don't think the declaration of LPM_MULT is the key question. The key problem is the LPM_MULT doesn't work in modelsim, but has no problem in quartus. By the way, how to check my LPM_MULT port is right or wrong? my quartus version is 8.1 and modelsim version is 6.5a .thanks for your reply

Altera_Forum · ‎11-26-2011

I just used megawizard for lpm_mult and here is the component as written by tool.

The tool adds one more file (wrapper). There is no point in preferring your instantation over that of tool. After all it is really a matter of hacking the tool.


lpm_mult_component : lpm_mult
    GENERIC MAP (
        lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5",
        lpm_pipeline => 1,
        lpm_representation => "SIGNED",
        lpm_type => "LPM_MULT",
        lpm_widtha => 8,
        lpm_widthb => 8,
        lpm_widthp => 16
    )
    PORT MAP (
        clock => clock,
        dataa => dataa,
        datab => datab,
        result => sub_wire0
    );

The question is why you got more ports and what is L_mult ??

Altera_Forum · ‎11-26-2011

--- Quote Start ---

I want to use the dedicated multiplier but reluctant to use ip core, which generates too much files, so writed the vhdl code. I don't think the declaration of LPM_MULT is the key question. The key problem is the LPM_MULT doesn't work in modelsim, but has no problem in quartus. By the way, how to check my LPM_MULT port is right or wrong? my quartus version is 8.1 and modelsim version is 6.5a .thanks for your reply

--- Quote End ---

But the LPM mult IS an IP core, whether you use the megawizard or instantiate it yourself, its the same thing.

a <= b * c; will also use the dedicated multipliers. The advantage with this is its much less code, and you dont have to use std_logic_vectors (which are not meant for arithmatic) to do it (you should use signed and unsigned types).