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Altera_Forum
Honored Contributor II
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library ieee; 

use ieee.std_logic_1164.all; 

use ieee.std_logic_unsigned.all; 

entity Ttrigger2 is 

port(t,clk:in std_logic; 

q:buffer std_logic); 

end Ttrigger2; 

architecture b of Ttrigger2 is 

begin 

signal qq:std_logic; 

process(clk) 

begin 

if t='1' then qq<=not qq; 

else qq<=qq; 

end if; 

end process; 

q<=qq; 

end b; 

Error (10500): VHDL syntax error at Ttrigger2.vhd(10) near text "signal"; expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement
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Altera_Forum
Honored Contributor II
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Move the line signal qq:std_logic; between architecture and begin. 

In addition, you should use a if rising_edge(clk) condition, otherwise that code won't work.
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Altera_Forum
Honored Contributor II
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you really should be fixing syntax problems yourself. Have you got a VHDL tutorial?

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Altera_Forum
Honored Contributor II
216 Views

thank you two.i have a vhdl book.forgive me. tomorrow i have a vhdl exam and i'm anxious .

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