about component

[Altera_Forum]

library ieee; 

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mand2 is port( a,b:in std_logic; c:out std_logic); end mand2; architecture bb of mand2 is begin c<=a and b; end bb;    use work.mand2.all; library ieee; use ieee.std_logic_1164; entity p60 is port(x,y:in std_logic; z:out std_logic); end p60; architecture b of p60 is component mand2 port(a,b:in std_logic; c:out std_logic); end component; begin mand2 port map(a=>x,b=>y,c=>z); end b; Error (10500): VHDL syntax error at p60.vhd(14) near text "port"; expecting "(", or "'", or "." i really can't understand that error.

[Altera_Forum]

help&#65292;i have the vhdl term exam 1 hour later.thanks for everyone's attention.

[Altera_Forum]

All the questions you have easily find an answer in any VHDL book... to instantiate a component the syntax is: 

Label: componentName generic map (...) port map (...);

[Altera_Forum]

thank you.when i add the Label,quartus ii reports error again. 

Error (10800): VHDL error at p60.vhd(1): selected name in use clause is not an expanded name. but i've already add mand2.vhd to the current project.

[Altera_Forum]

use work.mand2.all; 

 mand2 is not a package, so you cannot "use" like that. You dont need this line.

[Altera_Forum]

Thank you.