one shot and D flip flops

[Altera_Forum]

Greetings. 

 What is the advantage of putting one shots (one clock pulse if the D in a flip flop goes high) and basic D flip flops in designs? I see them placed in a lot of designs I look and and wonder if there are certain rules experienced designers use for them. When would be a good time to use a "Oneshot" or a "D flip flop"   Thanks

[Altera_Forum]

using the outputs of logic/registers as clocks is a general no-no in FPGAs. You CAN do it, but unless you get the "clock" into a clock net you're going to have timing problems. 

 Its best to use clock enables (and much less complicated and much easier for another engineer to understand.)

[Altera_Forum]

What is then the best use for D flip flops in a design?  

 thanks for the reply

[Altera_Forum]

basically everything involving a clock. They create the pipeline 

 D types are the basis of all designs. You can use clock enables to move data along the pipeline or not.