How to enable LE usage when implementing FIFO

[Altera_Forum]

Hi Dears: 

 I'm using ArriaGX FPGA devices and there are many small fifo blocks will be used in my project. So i want to implement these samll fifo using LE and save RAM. I remenber that i can enable this option in older version QII, but can't enable this option in 11.0 version as attached image file shown now.  There is a option in 11.0, but it's gray and not be used for user.

[Altera_Forum]

You should still be able to do it, but the option moved to the last page Optimization, Circuitry Protection: Implement FIFO storage with logic cells only, even if the device contains memory blocks. It'll grey out too when you enabled certain signals in DCFIFO2 (I think it was "Add an extra MSB to usedw port(s)"), which I think is a bug though. Anyhow, that's the way to do it, at least I hope so, as I need to implement several smaller FIFOs and do not have any spare M9K to waste for it, but lots of registers.