SignalTap 11.0 enters infinite loop with negative array indexes

[Altera_Forum]

Just reporting a bug. It was really my fault, but it's clearly a corner-case that Altera has not considered with SignalTap. 

 SignalTap will enter an infinite loop if you attempt to add (in the "Setup" tab, "SignalTap: pre-synthesis" selected for signal search) a verilog array which has a negative index. Ate up my entire 8GB of system memory. :) Haha. Anyway, should be a really easy bug fix if the right person at altera reads this. Not sure if it happens in the latest version of Quartus.  Here is the code that caused the bug (C_NUM_BITS was set to 0 by mistake, it should have been 1):  `define C_NUM_BITS 0 output reg [`C_NUM_BITS-1:0] my_reg;  The Quartus compiler generated a valid programming file but it did say: ; my_reg[-1] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;  So quartus handled it just fine, but SignalTap lost it's mind and started eating my machine. Hehe.

[Altera_Forum]

nice find! could you file a bug at http://mysupport.altera.com?

[Altera_Forum]

Sure, I can do that. But I was under the assumption that Altera isn't going to accept bug reports from non-subscription/non-paying customers. Am I wrong? I'm just a lowly web-edition user.

[Altera_Forum]

understandable, but i do think they will file a bug report even from Web Edition users. it sounds easily repeatable so that's also a plus

[Altera_Forum]

Altera is supporting all registered customers independent of a software subscription status as far as I'm aware of. In fact, professional customers don't necessarily own a personal software subsription, it would be unwise not to listen to their questions.

[Altera_Forum]

Okey-doke, I submitted the case. Will be interesting to see if anyone contacts me.

[Altera_Forum]

To my surprise, Altera support replied to my case. :) This bug was actually a known issue in 11.0. It has since been fixed in 11.1+. Regards, Jonathon