Storing data in array

[Altera_Forum]

Hi, 

 I wrote a simple code for multiplication and wanted to store the result in an array. The code does not show any error during compilation, but the output is zeros. Could some one tell me why I am unable to store the result in array. The code is as follows.  always @(posedge clk) begin   for(i=0;i<5;i=i+1) begin temp= x*h[i]; end  y=temp[0]+temp[1]+temp[2]+temp[3]+temp[4]; out[n]=y;  n=n+1'b1; end endmodule   "Y" is my actual output and out is a register (array) in which I would like to store the result of y. When I run this code, the value of y is displayed, but out is zeros. counter "n" is a register.  I would appreciate any suggestions regarding this.   Thank you, Ambrin

[Altera_Forum]

Did You simulate the design?

[Altera_Forum]

Yes. I simulated in Modelsim.

[Altera_Forum]

Try to do the same without using the for structure.

[Altera_Forum]

Hi Aprado, 

 Now the result in stored in array if I don't use for structure.  But could you explain why this happens only without for structure. Also I am actually designing FIR filter which is supposed to have 100 coefficients. That is why I used for structure, because without that I will have to manually write 100 multiplications.  I appreciate your help.

[Altera_Forum]

There's no obvious reason for failure of your code. But you're showing only a snippet and there may be trivial problems like not initializing n. 

 If you extend the code to 100 multiplications (and respective additions), it will hardly synthesize with resonable clock speeds without pipelining the adders.

[Altera_Forum]

As far as i know FOR shouldn't be used in hardware.. BUT the way you are using is pretty much like a FOR GENERATOR in VHDL which works fine (at least in VHDL it is the equivalent of expanding the code) 

 You might be using the for in an unaproriated way (i am working more with VHDL lately and i've never used FOR in verilog)

[Altera_Forum]

Loops can be easily used in designing hardware, because synthesizer will unwrap the loop and do the synthesis with all the possible loop variable values.

[Altera_Forum]

--- Quote Start ---  In a HDL (hardware definition language), iteration schemes have a different meaning than in procedural programming languages. They don't define sequential processing of the included statements but are a method to define parallel processing. Even if the iteration construct would be accepted by the Veriolog compiler (when using constant loop parameters), the resource requirement would go beyond any meaningful FPGA size.   --- Quote End ---   By FVM in another thread. Yeah, it will just unwrap the loop.. so the loop needs to be finite, have a low size and to be constant. It is unrolled BEFORE synthesis