“Cannot convert all sets of registers into RAM megafunctions when creating nodes.”

[Altera_Forum]

hi all, 

 I'w created a design (using a custom ip path at the toplevel) and was able to generate/compile my design using Quartus II.    However, when I add a a second instance of my custom ip path I get the error message:   error: cannot convert all sets of registers into ram megafunctions when creating nodes. the resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. this can cause longer compilation time or result in insufficient memory to complete analysis and synthesis.   In order to get rid of the error message I tryed replacing all 2 port RAMS in my custom IP path with the Megawizard Plug-In Manager 2-PORT RAMs. This did not help, as the error message still persists.   I would be thankfull for some advise here

[Altera_Forum]

Go to the Project Navigator(hierarchy browser) in top-left and right-click to make sure dedicated logic registers is shown, or resources per entity in the map report(due it in the GUI so you can collapse/expand leaves). They will show number of registers within a hierarchy and in parentheses, how many are in that hierarchy. This should help you find the problem. (Also, is the number of registers it's creating way off from what you would expect?)

[Altera_Forum]

hi again,  

 thank you for your reply.    I was already looking at the resource usage in the hierarchy tab as I was trying to increase the usage of M9Ks blocks instead of the synthesis tool using internal logic/register resources in the FPGA.    Your pointer with regard to the Dedicated Logic Registers was helpfull, I commented out a couple of the modules in my custom IP path that are using the Dedicated Logic Register resources and was able to compile my design using two custom IP paths.    From what I can see in the Hierarchy tab, the QSYS design is by far the biggest consumer of Dedicated Logic Register (see attachment), and IP's such as the altmemddr and the two scaler in the QSYS design are major contributers. In comparison, the custom IP's are modest users of the Dedicated Logic Registers resource.   Are there any steps that can be taken inorder to reduce the usage of the Dedicated Logic Registers ?

[Altera_Forum]

Unlikely. Registers are really the stakes in your design that get it to work. You can't remove registers and have the same functionality. (The exception being memories or large shift-registers that can go into dedicatd memory blocks, which then have the same functionality). The report looks good. I don't know what device you're targeting, but if it's not fitting, I don't think it's a register problem, but just too much logic for the device. Look at Tools -> Advisors -> Area Optimization Advisors for settings to make it smaller, but these usually don't have too profound of an effect. To really reduce the area, you need to remove logic/functionality.

[Altera_Forum]

hi, 

 The error message I was getting was'nt that clear, as I'm probable hitting the ceiling with regard to the FPGA logic resource.   For now I did make some changes inorder to optimize the area usage using the Tools -> Advisors -> Resource Optimization Advisors, but I have yet to see how this will affect the design.   Also, for the custom IP modules I guess I'll try to be more aware of the (V)HDL coding with regard to area utilization, not declearing excesively large registers, making more efficient code etc.   At the moment I'm using the Cyclone III development board (using the Cyclone III EPC120 device), but I will shortly be switching to the DE3-150 development board (using the Stratix III 3SL150 ) which has more resources available.      regards    Saber890