HDL sentences skills

[Altera_Forum]

hi : 

I have read the HDL sentences as below,the two HDL sentences seems as feedback :the signal "Busyhold_clkB” at right in the first sentence show up at left in the second sentence,at the meantime, the signal “TaskBusy_clkB” at right in the second sentence show up at left in the first sentence.I wanna know how to understand the skills.   1:assign TaskBusy_clkB = TaskStart_clkB | Busyhold_clkB; 2:always @(posedge clk) Busyhold_clkB <= ~TaskDone_clkB & TaskBusy_clkB;     thanks ~

[Altera_Forum]

Busyhold_clkB is a sort of system status which you set or reset 

by respectively pulsing TaskStart_clkB or TaskDone_clkB. Busyhold_clkB will keep the last value indefinitely until the next pulse is received.

[Altera_Forum]

thanks for your reply~ 

I seems understand what you said, maybe I can change the above sentance like this:   always @(posedge clk) Busyhold_clkB <= ~TaskDone_clkB & (TaskStart_clkB | Busyhold_clk);   ——> A <= C & (B | A);   signal A set after meeting high level B,and keep high indefinitly.then the signal C will used to reset A.

[Altera_Forum]

--- Quote Start ---   ——> A <= C & (B | A);    --- Quote End ---   Yes, that's the same, although in your original code C signal logic was inverted, namely A <= ~C & (B | A); Please note that the above line must be included in a always @(posedge clk) statement.  I guess your concerns are on the difference between assign and always statement. You'd better refer to a Verilog manual, which is more reliable and detailed than me :p. Anyway, in a few words: - this is not C programming; hdl functions are evaluated in parallel, not in a sequential way - assign dictates an operation to be performed continuously, independently from clock and where the statement is placed; you can place it before or after the always process which needs it, but the result would still be the same. An assign is generally synthesized in a combinatorial logic chain.  - always @(posedge clk) means the following operations are to be executed only when a positive edge is detected on clk signal; this involves use of flip-flops during synthesis.