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Does anybody use this chips? They have unmatched package specification in early and current documentation. There are VCC Bus surrounding GND pad in early docs, but it doesn't exist in current specification.
This space would be very useful in case of bus absent for via placement, however I can't find Altera recommended footprint and/or layout recomendations for this case. I have EP4CGX15BN11C8NES chips - they have such bus. Does this bus absent in mass production devices ? Does anybody have Altera recommended footprint for this device ?Link Copied
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--- Quote Start --- Does anybody use this chips? They have unmatched package specification in early and current documentation. There are VCC Bus surrounding GND pad in early docs, but it doesn't exist in current specification. This space would be very useful in case of bus absent for via placement, however I can't find Altera recommended footprint and/or layout recomendations for this case. I have EP4CGX15BN11C8NES chips - they have such bus. Does this bus absent in mass production devices ? Does anybody have Altera recommended footprint for this device ? --- Quote End --- You have EP4CGX15BN11C8Nes chips. These are "Engineering Samples", so You may have special chips that are not released to the market.
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--- Quote Start --- You have EP4CGX15BN11C8Nes chips. These are "Engineering Samples", so You may have special chips that are not released to the market. --- Quote End --- I've checked parts again. I was wrong - it's C8N chips (not ..ES). So it isn't special chips.
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Then the pinout should be identical to the pinout shown in Pin Planner.
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Did you review the Quartus *.pin file? There should be also pinout Excel and PDF documents.
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