VHDL compiler

[Altera_Forum]

Hi , 

 Is there a VHDL compiler that will compile the code and translate it into a schematic with primitive components . I have used Quartus and Xilinx their compliers synthesize away some parts of the code and also they use their mega cores .    I just need to see what my VHDL code translates to , irrespective of what FPGA i am targeting.   Thanks

[Altera_Forum]

Megawizard IP cores are only present if you instanatiate them. The synthesis tools don't magically inject megawizards, instead they map your HDL to FPGA primatives like multipliers, RAMs, LUTs, etc... The synthesized results are different since they are different technologies and a different set of primatives. 

 So what are you trying to do since I'm scratching my head wondering why someone would want to do this?

[Altera_Forum]

When i compiled this vhdl file , quartus showed these figures one is RTL and other is Post Map . I understand the compiler used LUT in Post Map in order to make it faster and also it doesnt consume any FF. The code was for a simple up counter , what i wanted to see at least at RTL level was the Counter Schematic . 

 See files attached .

[Altera_Forum]

To be clear really the only schematic is that last screenshot you attached. The other two are really just representations of the logic. The LUT is not an optimization, it *is* the implemation of your combinational logic since FPGAs do not have primitives like AND, OR, and NOT gates. instead lookup tables are used where the inputs of your logic wire up to the LUT address line, and the LUT itself is populated with all the possible combinations of outputs. This is not specific to Altera FPGAs, this is how FPGAs work in general. If you look at the device handbook and study the LE or ALUT structure this will probably make more sense.

[Altera_Forum]

I think Bad Omen has covered your question, but Id like to point out several problems with your code: 

 1. You should no use std_logic_arith and numeric_std in the same bit of code. They conflict. You should use the standard numeric_std rather than the non-standard std_logic_arith.  2. cont is missing from the process sensitivity list. THis is going to create a missmatch between simulation and reality (as the synthesisor ignores the sensitivity list). Also, you cannot write the code the way you have because you are asking it to count infinitly quickly if KEY(1) = '0'. You need a clock in your circuit for a counter.  3. The LEDG assignment should be outside the process.

[Altera_Forum]

Badomen you are right , i think i didnt use the right word, the compiler didnt optimize it, it just implements the combintorial logic' truth table into a LUT . This bring me back to my original question i want to see the combintorial logic , i need a compiler that shows me that instead of LUT's . 

 The Schematic "Counter_Schenatic" is made by me manually .   Tricky the answer to your reply is , i connected it to KEY(1) to test it on board , yes i should have used clock and divide by 50 to see the LEDS blinking . This was just a test to see DE2-115 works .   Regards ,

[Altera_Forum]

I don't know of any tools that can take HDL and turn it into a schematic. Quartus II can perform the opposite conversion though. The RTL viewer view is the closest you'll get to this but like I mentioned before it's just showing you the functional equivalent of how it is actually implemented in the device. 

 Sometimes I perform HDL to schematic conversions to get a better understanding of the functionality but I do this manually with the assumption that it's just a functional equivalent and it is not really how it would be implemented in any real device (FPGA or ASIC). If this wasn't the case then we wouldn't need synthesis tools and chips would take forever to design as a result. After I complete that then I normally switch back to my usual "how many LUTs wide and deep would this logic be?" mode since I typically optimize my HDL knowing it's going into an FPGA.

[Altera_Forum]

--- Quote Start ---  I understand the compiler used LUT in Post Map in order to make it faster and also it doesnt consume any FF. The code was for a simple up counter , what i wanted to see at least at RTL level was the Counter Schematic.  --- Quote End ---     --- Quote Start ---  Tricky the answer to your reply is , i connected it to KEY(1) to test it on board , yes i should have used clock and divide by 50 to see the LEDS blinking . This was just a test to see DE2-115 works .  --- Quote End ---   But it doesn't work, at least not count regularly. A combinational counter description can't be synthesized to any meaningful FPGA logic. That's why you see only gates (LUT) instead of FFs.   In my opinion, both Quartus RTL and gate level schematics are more or less readable. I'm inspecting it frequently to reveal possible design errors. In the present case, the RTL schematic has all necessary information to see, that the design doesn't work as a counter. With some VHDL experience, you see it from the VHDL text as well.

[Altera_Forum]

But it doesn't work, at least not count regularly. 

what do you mean the code or the design ??    A combinational counter description can't be synthesized to any meaningful FPGA logic. That's why you see only gates (LUT) instead of FFs.    Well the compiler just looks at the truth table and for all the possible logic inputs synchronized with rising edge , connects the gates in the LE so that LUT can output that specific reponse. Just like in Karnapgh mapping .   but when i complied the schematic i got the same RTL as the shematic .  Also i wanted to edit my 4-bit counter to count down , guess what in altera components all types of FF have only "Q" output , they are without "/Q" output .