Verilog "case" collision problem

[Altera_Forum]

case( 1'b1 ) // synthesis parallel_case 

a:value <= 4'd1; b:value <= 4'd2; c:value <= 4'd3; d:value <= 4'd4; endcase  if there is only 1 condition equals,the synthesis result is parallel. My question is:when there are 2 or more condition hit,for example,b=1 and a=1,How the "value" turn out to be? It's 4'hxx or 4'd2 ? Does the value depend on the first statement when multiple hits?  thank U!

[Altera_Forum]

your case statement must cater for all cases including default. 

So your question is not right. Your case variable cannot have two values at same time.  Edit: looks like your case statement is upside down

[Altera_Forum]

actually,in my design,there are 8 case variables ,so if I use the priority structure like "if(a==1)..else if(b==1)...else if(c==1)...",the path delay will be very long! 

So I want to use the parallel structure as above described. "looks like your case statement is upside down"----I have tested the codes,it will be synthesised as parallel circuit because of the "synthesis parallel_case" .

[Altera_Forum]

If you mean your case subject is 8 bits then you can say: 

 case subject "00000000": do this "00000001": do that ...etc  you may use better syntax than me as my Verilog is rusty.