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Trying to simulate the project seems to have caused license issues. Before simulation the project would compile and download ok.
Tried to simulated from the menue tools->run simulation tool. This failed, and told me to see a rpt file, which said license was not available for a mega function. After this the project no longer compiles - there is an error "Error (204009): Can't generate netlist output files because the license for encrypted file "D:/projects/software/yuv2rgb/altera/fifo_ddr/auk_ddr_hp_controller.vhd" is not available Can anyone shed light on what needs to be done to fix this? Thank you! SteveLink Copied
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you'll be able to configure an FPGA with an IP that you do not have a license, this is known as the OpenCore Plus feature
you'll also be able to simulate the core using the .vo/.vho file for most IP - though the memory IP uses source HDL for simulation, not a .vo/.vho netlist. follow the directions for simulating the example design in the User Guide i don't think you'll be able to do a full chip simulation: No .vqm, or atom-level .vo, or .vho files are generated. http://www.altera.com/literature/an/an320.pdf- Mark as New
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Thank you for the help! Not trying to simulate anymore, just compile - works fine now.
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