Obscure ModelSim error

[Altera_Forum]

I have come across this Modelsim error a few times now: 

Using the Nativel Link RTL simulation - Quartus 11.1sp1 Web Edition. # ** Fatal: Unexpected signal: 11. # ** Error: C:/qdesigns/bv5fpga/bb/ImageDataDispatch/iddRamRead/iddRamRead.vhd(208): VHDL Compiler exiting # ** Error: C:/altera/11.1/modelsim_ase/win32aloem/vcom failed. I then usually just switch to Gate Level Timing simulation, but today I have to do a 'long' simulation and I'd like to add RTL signals to the signals pane rather then adding the singular post mapping signals. Any clues here?

[Altera_Forum]

the first line leads me to believe that there's a port/signal/variable that begins with a 11, which i thought Quartus would flat as being illegal VHDL

[Altera_Forum]

--- Quote Start ---  the first line leads me to believe that there's a port/signal/variable that begins with a 11, which i thought Quartus would flat as being illegal VHDL  --- Quote End ---    If it were that easy I wouldn't have come here!  Anyway I ran Quartus Synthesis first, as you have to before you can start the testbench writer.

[Altera_Forum]

it doesn't hurt to check the obvious 

 you might try opening ModelSim without invoking it through NativeLink and try compiling the iddRamRead.vhd itself  what's on line 208 of the mentioned file?

[Altera_Forum]

--- Quote Start ---  you might try opening ModelSim without invoking it through NativeLink and try compiling the iddRamRead.vhd itself  --- Quote End ---   I only recently started using ModelSim in lieu of the internal simulator, the NativeLink is nice as I do all VHDL work inside Quartus. I'll give your suggestion a try.    --- Quote Start ---  what's on line 208 of the mentioned file?  --- Quote End ---   the final 'end architecture ;'

[Altera_Forum]

I opened ModelSim directly and created a project and add the necessary files. But it chokes on that same file with the same error message. I played around with the options disabling optimizations etc. but to no avail. It obviously is a problem with the ModelSim VHDL compiler that doesn't handle everything the Quartus Synthesiser has no prblem with. Is there a possibility to pipe the output of the Qaurtus Synthesis into Modelsim? Else I guess I'll have to do with the Gate Level Simulation.

[Altera_Forum]

--- Quote Start ---  I opened ModelSim directly ... But it chokes on that same file  --- Quote End ---    Post the file. Perhaps a manual parsing of the source will expose the error.  I've done stupid things like having a port named 'delay' on a component named 'delay' (or something like that), which yields completely bogus syntax errors.  Cheers, Dave