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hello everyone, i am trying to do a frequency divider which convert 33.333Mhz to 1hz frequency, the code don't show any error after compilation, but my result is all zero after simulation. can anyone please help me
the following is the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity clk_gen is port( Clk : in std_logic; Clk_mod : out std_logic ); end clk_gen; architecture Behavioral of clk_gen is signal clkdiv : unsigned(24 downto 0); signal clk1hz : std_logic; begin process(Clk) begin if rising_edge (Clk) then clkdiv <= clkdiv + 1; end if; end process; clk1hz <= clkdiv(24); Clk_mod <= clk1hz; end Behavioral;Link Copied
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The simulator does not know the value for clkdiv, so how does it know where to start?
Either add a reset to the process, or start clkdiv at zero using: signal clkdiv : unsigned(24 downto 0) := (others => '0'); Cheers, Dave- Mark as New
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Besides what Dave correctly suggested, I remark that you need up to 2^23 clk cycles before you get a non-zero output.
This might require a somewhat long simulation time. Have you considered it? For easier preliminary testing with simulator you'd better temporarily use a lower ratio, e.g. clk1hz <= clkdiv(8);- Mark as New
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--- Quote Start --- Besides what Dave correctly suggested, I remark that you need up to 2^23 clk cycles before you get a non-zero output. This might require a somewhat long simulation time. Have you considered it? For easier preliminary testing with simulator you'd better temporarily use a lower ratio, e.g. clk1hz <= clkdiv(8); --- Quote End --- I try already, but still get the same result, zero, i even try for clk1hz <= clkdiv(2);...also same zero, is anywhere of my code wrong already?
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--- Quote Start --- The simulator does not know the value for clkdiv, so how does it know where to start? Either add a reset to the process, or start clkdiv at zero using: signal clkdiv : unsigned(24 downto 0) := (others => '0'); Cheers, Dave --- Quote End --- thanks for reply.. but i still get the same result, zero... is anywhere of my code wrong already?
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where is your testbench code?
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--- Quote Start --- For easier preliminary testing with simulator you'd better temporarily use a lower ratio, e.g. clk1hz <= clkdiv(8); --- Quote End --- I'm impatient, and I don't like editing code, so I use generics when I need something to happen faster in simulation than in real life :) Here's a modified version of your code (directed entered into this response, so its your job to fix any bugs);
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity clk_gen is
generic (
frequency : real := 33.333e6;
delay : real := 0.5
);
port (
rstN : in std_logic;
clk : in std_logic;
q : out std_logic
);
end entity;
architecture Behavioral of clk_gen is
-- Counter count
constant CVALUE : real := delay*frequency;
-- Counter width required
constant CWIDTH : integer :=
integer(ceil(log2(CVALUE)));
signal clkdiv : unsigned(CWIDTH-1 downto 0);
begin
process(Clk, rstN)
begin
if (rstN = '0') then
clkdiv <= (others => '0');
elsif rising_edge (Clk) then
clkdiv <= clkdiv + 1;
end if;
end process;
q <= clkdiv(CWIDTH-1);
end architecture;
When simulating in Modelsim, you can override the delay to something shorter. Cheers, Dave
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This is a 2hz frequency divider right?
33,3 * 10^6 / 1<< 24 is 2 And i suppose you are not using this as a clock for something..- Mark as New
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--- Quote Start --- where is your testbench code? --- Quote End --- I did't write test bench code, i just use simulation tools to test my result.. I thought quartus2 cannot write test bench?
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How are you simulating it then?
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--- Quote Start --- I did't write test bench code, i just use simulation tools to test my result.. I thought quartus2 cannot write test bench? --- Quote End --- Its up to you to write the testbench. Use this as an opportunity to learn. Look, lots of people are helping you already! Try and create a testbench, and post the code, along with questions, when you have trouble. Start with the example I posted here: http://www.alteraforum.com/forum/showthread.php?t=32386 Cheers, Dave
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--- Quote Start --- Its up to you to write the testbench. Use this as an opportunity to learn. Look, lots of people are helping you already! Try and create a testbench, and post the code, along with questions, when you have trouble. Start with the example I posted here: http://www.alteraforum.com/forum/showthread.php?t=32386 Cheers, Dave --- Quote End --- ok..then i try my best....thanks for helping me...
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