Library in QSYS

[Altera_Forum]

Hello everybody, 

 I've got a bit silly question about using QSYS.  I usually work with several libraries. Each library contains a top representing an IP (such as, for example, MedianFilter IP in medianfilter_lib, UART IP in uart_lib, ...) When I use QSYS to integrate this IP, the .QIP file generated by QSYS mentionned for all IP 'lib_system' as the requested library... but in my cases, it is either medianfilter_lib, ... The result is that the analysis&elaboration process in Quartus fails (design library medianfilter_lib does not contain primary unit medianfilter_top).  Do you have any workaround?  Many thanks!

[Altera_Forum]

In the _hw.tcl file add the libraries, eg., here's the files I need for my SRAM controller: 

  add_file ../../packages/src/utilities_pkg.vhd {SYNTHESIS SIMULATION} add_file ../../packages/src/altera_avalon_pkg.vhd {SYNTHESIS SIMULATION} add_file ../src/avs_sram_fsm.vhd {SYNTHESIS SIMULATION} add_file ../src/avs_sram.vhd {SYNTHESIS SIMULATION}   I suspect that your problem is you have added only the source for your component, and have not listed the libraries it uses.  Cheers, Dave

[Altera_Forum]

I absolutely agree with you but how do you associate a module (or a file) with a library that will be used in the .QIP file generated by QSYS in such a way that you will have: 

set_global_assignment -name VHDL_FILE -library sdramcontroller_lib   and not  set_global_assignment -name VHDL_FILE -library lib_system

[Altera_Forum]

--- Quote Start ---  I absolutely agree with you but how do you associate a module (or a file) with a library ...   --- Quote End ---  Hmm, good question.  I haven't used Qsys a great deal. However, in SOPC builder I found that VHDL libraries were not well supported. I just looked at the add_file documentation, and it does not have an option for the library in which to compile it.   I also found that the automatically generated instances always missed the lines:  Library mylib; using mylib.mycomponent.all;  So I resorted to using the callbacks to create my own top-level instances. Quartus does not complain about these missing library calls, but Modelsim does.  I'm not sure if this 'feature' has been carried through to Qsys.  Cheers, Dave

[Altera_Forum]

i've found Quartus VHDL library support to be poor in general

[Altera_Forum]

Ok, many thanks for your 2 answers... 

 I found a solution: I use a .QIP file so as to list all requested VHDL files  My new _HW.tcl:  ... add_file module_name.qip {SYNTHESIS SIMULATION} ...I create a module_name.qip file:  set_global_assignment -name VHDL_FILE -library common_lib set_global_assignment -name VHDL_FILE -library module_lib set_global_assignment -name VHDL_FILE -library module_lib set_global_assignment -name VHDL_FILE -library module_lib

[Altera_Forum]

Just wanted to mention that I had strange problems with Analysis&Synthesis of a project with a generated Qsys component, and I believe my problems could be attributed to the library handling as well. 

 For a Qsys custom component, I had stuff defined in a package (which is often necessary, with no workaround) and accessing packages need explicit library specification (use work.mypackage; etc). This usually works fine (for some reason, Quartus still finds the package althogh the generated Qsys system will place all units in a specific Qsys library), but I had one persistent error were something went wrong. It turned out that Analysis&Synthesis was unable to call a function in the custom package (the function was used to provide the actual for a generic).  I finally could work-around this by declaring a constant in the package, initializing the constant with the function (in the same pakcage), and provide the actual from that constant. In this way Analysis&Synthesis called the package function during package elaboration, not when elaborating the entity that needed the value.  My suspicion that this was a VHDL library issue is strengthen by the fact that instantiating the component directly in the Quartus project, rather than have it generated by Qsys, worked fine.