TimeQuest Constraint on PLL

[Altera_Forum]

I have a fairly trivial .sdc file which works with the following code: 

# Constrain the external FPGA clock from oscillator create_clock -period 20 -name clk [get_ports CLK]# Derive pll clocks & clock uncertainty derive_pll_clocks derive_clock_uncertainty  Now, I tried the following code and simply will not work. # -------------------------------------------------------# Constrain the Phase Locked Loop Master Clock = 50 MHz# ------------------------------------------------------- create_generated_clock -add  -source Upll|altpll:altpll_component|PLL50_LOCK_altpll:auto_generated|pll1|inclk[0]  -name Upll|altpll:altpll_component|PLL50_LOCK_altpll:auto_generated|pll1|clk[1]  -master_clock clk  [get_pins Upll|altpll:altpll_component|PLL50_LOCK_altpll:auto_generated|pll1|clk[1]]  Now, in the above code (which is downsized font to make it fit on screen), I am referencing a PLL which I am instantiating with VHDL that was generated from the Mega Wizard.    Upll: entity work.pll50_lock(syn)  port map (  inclk0 => inclk0,  c0 => clk1MHz,  c1 => c1,  locked => locked  );  I have read Altera's documentation carefully . . . . and find the TimeQuest documentation to be vague on the naming conventions. The example given with a symbol rather than verilog or VHDL example is quite trying.   I am wondering if anyone can see the problem with my code above to manually constrain the PLL clock.   Thank you. James

[Altera_Forum]

What do you mean it doesn't work? 

Doesn't derive_pll_clocks already constrain this PLL output? Why are you adding another one? If it's a syntax issue, then in TimeQuest messages, go to the derive_pll_clocks and just copy from there, as it gives the exact syntax for constraining the PLL.  Right now your assignment is after derive_pll_clocks, so you're constraining something that already has a generated clock on it. Either put the "-add" option on your generated clock, although it will need a different name, or put it before derive_pll_clocks, which won't constrain a PLL output if it already exists. The hierarchy names are annoyingly long, but you shouldn't ever have to enter them manually.

[Altera_Forum]

As I mentioned & declared previously, the code below DID WORK: 

   --- Quote Start ---  # Constrain the external FPGA clock from oscillator create_clock -period 20 -name clk [get_ports CLK]# Derive pll clocks & clock uncertainty derive_pll_clocks derive_clock_uncertainty  --- Quote End ---  The code below (separate from the code above, in its own SDC file) did NOT WORK:    --- Quote Start ---  #-------------------------------------------------------# Constrain the Phase Locked Loop Master Clock = 50 MHz# ------------------------------------------------------- create_generated_clock -add  -source Upll|altpll:altpll_component|PLL50_LOCK_altpll:aut o_generated|pll1|inclk[0]  -name Upll|altpll:altpll_component|PLL50_LOCK_altpll:aut o_generated|pll1|clk[1]  -master_clock clk  [get_pins Upll|altpll:altpll_component|PLL50_LOCK_altpll:aut o_generated|pll1|clk[1]]   --- Quote End ---  What I am really after is this: is the whole instantiation path necessary? It appears that it is, but even with that, I still would not work.   James

[Altera_Forum]

If they're independent files, then you're missing the create_clock. The generate clock has to be based off another clock.  

Assuming it's some of both, copy out of the TimeQuest messages from your derive_pll_clocks that worked. Derive_pll_clocks is not a real .sdc constraint, but a script that runs other .sdc commands. It tells you exactly what it ran, so if it worked, copy and paste from that. Besides the space in auto(which I assume is a cut and paste issue, as I've seen that here), you seem to be matching name conventions. You can either do entity:instance or just instance, i.e.: Upll:pll50_lock|altpll:altpll_component|PLL50_LOCK_altpll:aut o_generated|pll1|inclk[0] or pll50_lock|altpll_component|au o_generated|pll1|inclk[0] But in yours, it's using only entity on the top-instance and the PLL1 instance. Again, start with what derive_pll_clocks does.