Blocking/Nonblocking assignments in SystemVerilog always block

[Altera_Forum]

In Verilog, a commonly known rule states that in always blocks, only blocking or only nonblocking assignments should be used, not a mix in one block. 

Could anybody tell whether a similar rule is valid in SystemVerilog for always/always_comb/always_ff blocks? I have seen worked-out designs of an experienced designer and well known author of SV textbooks with a mixture of assignments type in one block, and I am not sure whether it is acceptable in SV, or, possibly, I do not understand something in this language that admits such use of assignments in SV blocks.  Thank in advance.

[Altera_Forum]

LRM says: The always_ff procedure imposes the restriction that it contains one and only one event control and no blocking timing controls. Variables on the left-hand side of assignments within an always_ff procedure, including variables from the contents of a called function, shall not be written to by any other process. 

 Software tools should perform additional checks to warn if the behavior within an always_ff procedure does not represent sequential logic.  A blocking assignment is not a blocking timing control. Blocking timing controls are# , @, wait, and task calls. Thus,  always_ff @(posedge clk) begin // LEGAL   logic temp;   temp=a && b; // local evaluation, for later usage   if(temp) c <= d;   end    always_ff @(posedge clk) begin // ILLEGAL   logic temp;   # 1 // <<<< ILLEGAL   temp=a && b; // local evaluation, for later usage   if(temp) e <= d;   end -------------------------------------------------------------------------- Ben Cohen (831) 345-1759  http://www.systemverilog.us/ ben@systemverilog.us  * SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7 * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0  * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8  * Component Design by Example, 2001 ISBN 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115 --------------------------------------------------------------------------