Fitter problem

[Altera_Forum]

Hi All, 

I have embarked on a project to develop a stopwatch which outputs seconds and minutes as a binary value. I am using two separate 8-bit LED boards connected to the MAX7000S EPM7128LC84-10 CPLD. I broke the project into smaller mini projects. The first being reducing the srystal oscillator frequency (25 MHZ) to 1 Hz. With Cris72’s help that works fine now. I then moved to the next phase of outputting the seconds and minutes to 2 separate LED boards. This program (shown below) works fine on the simulator however when I assign pins to the seconds vector I get loads of errors stating it cannot route all pins. Analysis and Synthesis is fine it’s a problem fitting my program into my hardware, I find it difficult to believe I have exceeded the user memory as I have not really got that many variables. Could I please trouble you for some advice on how I can overcome this problem? Thank you in advance :) PS: I have checked the seconds on an oscilloscope and they are accurate so the program works    -- Program to output seconds and minutes on 2 led boards. -- library declarations library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;   -- define input and outputs for the entity entity binstopwatch is port( clk_in: in std_logic; clk_out: buffer std_logic; secout : buffer std_logic_vector(7 downto 0);  minout : buffer std_logic_vector(7 downto 0);  clk: buffer std_logic); end binstopwatch;   -- Internal function of entity   architecture behave of binstopwatch is --internal 32-bit variable signal count: integer:= 1; signal clk_en : std_logic_vector (1 downto 0); begin process (count, clk_in,clk_out,clk_en) begin -- Required in order to convert the crystal Oscillator output to a square wave clk_out <= not clk_in; -- Check for rising edge of clock  if(clk_out'event and clk_out='1') then  --increment the count variable by 1  count <=count+1;  -- When count is half the clock frequency   if(count = 12500000) then  -- 0.5 Second high/low genaration  clk <= not clk;  clk_en<=clk_en + '1';  --reset count  count <= 1;  if(clk_en = "01") then  secout<=secout+1;  clk_en <= "00";  if(secout= "00111011") then  minout <=minout+1;  secout <="00000000";  if(minout = "11111111") then  minout<="00000000";  end if;  end if;  end if;  end if;  end if; end process;   end behave; 

[Altera_Forum]

I don't know much of MAX7000S but it's possible your design fits into the available logic elements but it requires excessive routing resources. In other words your MAX7000S has not enough wires inside to connect all the required signals. 

EPM7128 has 128 macrocells, namely 'only' 128 flip flops. I guess your design is using most of them; the interconnect matrix is probably quite loaded, too. In order to free some resources; I'd remove the following:  if(minout = "11111111") then  minout<="00000000";  end if; minout will automatically overflow to 0 after it has reached the all-1 state. You can also limit secout size to 6 bits, since the upper two are always 0.

[Altera_Forum]

Thanks a lot Chris, unfortunately I had to make seconds an internal signal so that it wouldn’t have to route is at all. I have now just minutes displayed on 1 LED board. On the plus side it is very accurate. I have an online stopwatch and the minutes match that perfectly. 

Thanks Chris J

[Altera_Forum]

Cris72 is correct the EPM7000S since it is macrocell based architecture it will be limited in routing resources. Furthermore, the macrocell architecture is not very scalable and therefore in the newer MAX II and MAX V it is FPGA based architecture with an internal flash for configuration.  

 /Boris

[Altera_Forum]

jag1972 to try to fit your design in the device I would optimize where you can. For example your minout and secout only needs to be 6 bits each since you only need to count to 60. This will save both registers and logic for the adder. Also, don't use a full 32 bit integer for the "count" it only needs 25-bits. This could also save some resources unless the tool is already optimizing it to that.  

 /Boris

[Altera_Forum]

Thank you Lethenstrom.  

Thank you very much for your advice. I did exactly what you said, however I was still getting routing problems. Therefore I reluctantly had remove the seconds display all together instead I have that pulsing on 1 led whilst the minutes count up to 120 on the same LED board. It works on the CPLD now. Thanks again :)

[Altera_Forum]

I am incredibly sorry to keep asking but I have again managed to hit a brick wall again. I am trying to develop a simple binary stopwatch using vhdl on quartus 2. I hope to download it into a CPLD. 

I would like to use 2 inputs, 1 input resets the count and the other pauses the program. I think I can do the first by using an if conditional statement in my process:  button: in std_logic vector(1 downto 0); This line will be in my entity  – In my process if (button1= “01”)  time<=”00000000” end if;   I am stuck on how to make the program pause ( button = “10”) and retain all values so that it can resume after an event (button “00”) . I can always prioritise for button”11”later.  I have been looking on the web and apparently I can not use a wait statement inside a process with a sensitivity list which is what I have. Could someone please offer me some advice.  PS: CPLD,s are annoying I have had so much grief trying to route (fitter problems).

[Altera_Forum]

You simply need to conditionate the count increment to the button status. 

For example, you can change the code you previously posted into: ... if(clk_out'event and clk_out='1' and button = “10”) then ...

[Altera_Forum]

Thank you very much Chris, it works fine now :)

[Altera_Forum]

thanks guys