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I'm designing in a situation where I will have limited HW multipliers on a Stratix IV (they're being used for other things). I know that Quartus knows how to generate the most efficient fixed-point multiplier using only ALMs because it does it in things like the FIR Compiler II.
Is there an easy way to either generate a MegaFunction or use a code directive to have iQuartus do the best it can without using a hard-block? Thanks! /jLink Copied
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IIRC, if Quartus runs out of multipliers, it should start making ALM versions for you. But if you want to select which multipler will use logic, in VHDL you can use attributes:
signal a, b : unsigned(8 downto 0);
signal res : unsigned(17 downto 0);
attribute multstyle : string;
attribute multstyle of res : signal is "logic";
res <= a * b;
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thanks tricky
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just FYI FIR Compiler II is quite smart and doing most of the heavy lifting with optimization, not Quartus. it's a very cool tool
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