Model a matching bit in Modelsim

Altera_Forum · ‎01-27-2012

Greetings I have to watch this bit of code below: It is a string of 20 bits that has a string of ten bits shifting through it trying to match it's ten bits within the 20 bit string. kind of like a key finding where it fits.

syn_frame_gen: for i in (9) downto (0) generate
syn_frame_vhdl: entity work.mycmp10_vhdl
    port map
        (d => d20s((9+i) downto (i)),
  d1 => "0101111100",--syn1
  d2 => "1010000011", --syn2
  match => ind_syn(i));
 
end generate syn_frame_gen;

Here is the item mycmp10

entity mycmp10_vhdl is
port (d,d1,d2   : in std_logic_vector(9 downto 0);
      match   : out std_logic);
end mycmp10_vhdl;
architecture rtl of mycmp10_vhdl is
signal d1equal, d2equal : std_logic;
    begin
      d1equal <= '1' when d1 = d else '0';
      d2equal <= '1' when d2 = d else '0';
      match <= ( d1equal) OR (d2equal); --need to simulate
end rtl;

I need a quick and easy way to flag this in modelsim everytime I get a match. How do I write a scrip to show something on the wave display that will let me know when a match is made.

Some sort of virtual signal or something? I am new to modelsim and cannot seem to dig the right stuff out of the manuals.

Thanks

Altera_Forum · ‎01-27-2012

You could add an assertion.


assert (match = '1')
    report "Match found!"
    severity note;

This will generate markers in the Modelsim wave window.

(Actually it might be match /= '1', since the assertion triggers when not true)

Cheers,

Dave