VHDL problem: inputs and constants

Altera_Forum · ‎01-29-2012

Hi all,

I've a problem in VHDL.

This code runs correctly:


library IEEE;
use IEEE.std_logic_1164.all;
entity CLOCK_SIM is
 generic
 (
  constant FREQ : integer:=10000000;
  constant DUTY : integer:=50
 );
 port
 (
  enable : in STD_LOGIC;
  output : out STD_LOGIC
 );
end CLOCK_SIM;
architecture CLOCK_SIM_ARCH of CLOCK_SIM is
begin
 -- Processo principale
 MainProcess : process
  constant RDUTY : real:=real(DUTY)/100.0;
  constant TCLKH : time:=1 sec*((1.0/real(FREQ))*RDUTY);
  constant TCLKL : time:=1 sec*((1.0/real(FREQ))*(1.0-RDUTY));
 begin
  if enable='1' then
   output<='1';
   wait for TCLKH;
   output<='0';
   wait for TCLKL;
  else
   wait until enable='1';
  end if;
 end process MainProcess;
end CLOCK_SIM_ARCH;

but if I make a constant like an input:


library IEEE;
use IEEE.std_logic_1164.all;
entity pwm_DC is
 generic
 (
  --constant FREQ : integer:=1000000;
  constant DUTY : integer:=50
 );
 port
 (
  f      : in integer;
  enable : in STD_LOGIC;
  output : out STD_LOGIC
 );
end pwm_DC;
architecture pwm_DC_arch of pwm_DC is
signal FREQ : integer;
begin
 FREQ <= f;
 -- Processo principale
 MainProcess : process  
  constant RDUTY : real:=real(DUTY)/100.0;
  constant TCLKH : time:=1 sec*((1.0/real(FREQ))*RDUTY);
  constant TCLKL : time:=1 sec*((1.0/real(FREQ))*(1.0-RDUTY));
 begin
  if enable='1' then
   output<='1';
   wait for TCLKH;
   output<='0';
   wait for TCLKL;
  else
   wait until enable='1';
  end if;
 end process MainProcess;
end pwm_DC_arch;

this is the error:

# ** error: (vsim-3601) iteration limit reached at time 7 us.

Can anyone help me?

Altera_Forum · ‎01-29-2012

You have two constants (tclkh and tclkl) that will depend on the value of a signal 'freq' which in turn depends on the value of another signal 'f'.

Fix that up by changing those two constants to signals and give it another go...a calculated constant can't depend on a signal, since a signal is not 'constant'

Kevin Jennings

Altera_Forum · ‎01-30-2012

Hi Kevin,

thanks a lot for your help.

I just don't know how to do this.

I have to change the 2 constants

constant FREQ

constant DUTY

into two input signals.

By these 2 signals, I can calculate these 2 values

TCLKH

TCLKL

which I use to generate the output signal, a square wave with a duty cycle that depends on my two input values.

Can you help me?

Altera_Forum · ‎01-30-2012

change TCLKH and TCLKL to signals or variables, and calculate their value at runtime, rather than at elaboration time. Currently, they use the initial value of FREQ, which will be -2^31.

Altera_Forum · ‎01-30-2012

Hi TRicky,

thanks to your help I solved the problem.

Here's the simple code:


library IEEE;
use IEEE.std_logic_1164.all;
entity pwm_DC is
 port
 (
  f      : in real;
  d      : in real;
  output : out STD_LOGIC
 );
end pwm_DC;
architecture pwm_DC_arch of pwm_DC is
begin  
 -- Processo principale: generazione Duty Cycle
 MainProcess : process
  variable FREQ  : real;
  variable DUTY  : real;
  variable RDUTY : real;
  variable TCLKH : time;
  variable TCLKL : time;
 begin   
   FREQ  := f;
   DUTY  := d;
   RDUTY := DUTY/100.0;
   TCLKH := 1 sec*((1.0/FREQ)*RDUTY);
   TCLKL := 1 sec*((1.0/FREQ)*(1.0-RDUTY));
   output<='1';
   wait for TCLKH;
   output<='0';
   wait for TCLKL;
 end process MainProcess;
end pwm_DC_arch;