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Dear friends
I am using Quartus II 11.1sp1 Web Edition. I am going to generate custom clocks around 10Hz - 100Hz; I have used altclklock Megafunction; However I get the following error during compilationError (15538): Can't implement PLL "altclklock:inst5|altpll:pll|altpll_n571:auto_generated|pll1" as Cyclone IV E PLL type
Error (15093): Can't implement clock multiplication and clock division parameter values for PLL "altclklock:inst5|altpll:pll|altpll_n571:auto_generated|pll1"
Error (15094): Can't implement PLL because Division and Multiplication cannot be achieved
Error (15532): inclk0 input frequency of 20000.0 MHz for Cyclone IV E PLL "altclklock:inst5|altpll:pll|altpll_n571:auto_generated|pll1" must be in the frequency range of 5.0 MHz to 472.59 MHz
How can I generate low frequency clocks?
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This is too slow for the pll. You should use a logic divider instead.
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--- Quote Start --- Dear friends I am using Quartus II 11.1sp1 Web Edition. I am going to generate custom clocks around 10Hz - 100Hz; I have used altclklock Megafunction; However I get the following error during compilation
Error (15538): Can't implement PLL "altclklock:inst5|altpll:pll|altpll_n571:auto_generated|pll1" as Cyclone IV E PLL type
Error (15093): Can't implement clock multiplication and clock division parameter values for PLL "altclklock:inst5|altpll:pll|altpll_n571:auto_generated|pll1"
Error (15094): Can't implement PLL because Division and Multiplication cannot be achieved
Error (15532): inclk0 input frequency of 20000.0 MHz for Cyclone IV E PLL "altclklock:inst5|altpll:pll|altpll_n571:auto_generated|pll1" must be in the frequency range of 5.0 MHz to 472.59 MHz
How can I generate low frequency clocks? --- Quote End --- If you're generating these low frequency clocks to use internally in your design, then the answer is that you should not generate these clocks at all. If these clocks are going out on pins and not used internally, then you should you a counter to generate the clocks instead. Kevin Jennings
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