AS and JTAG access to cyclone II device

[Altera_Forum]

Hello, I did a design that has both JTAG access and AS access to a single cyclone II device, and am looking to see if I did it correctly.  

 For the AS circuit, I just used the suggested circuit shown in figure 13-7 in the altera document:  http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf, except the msel pins are pulled low.   For the JTAG circuit I used the figure 13-22 of the same document.   Its just the same as the recommended circuitry, using 2 2x5 headers, except NCE is driven differently depending on which mode you are in. I used a SPDT switch to determine this mode.   When in one position (RUN or JTAG), it feeds a 0 to the NCE pin of the FPGA. If in the other position (PROG) it feeds PIN 6 of the AS header, which is also pulled-down through a 10k resistor.   Is this the correct way to have both JTAG and Active Serial access to the FPGA using a serial device? Also if I am using the byte blaster cable to do the AS programming, is it correct to use standard AS, or fast AS, as determined by the msel pins?  Thank you, any insight is very much appreciated!

[Altera_Forum]

Combination of AS and JTAG configuration schemes is described under "Combining JTAG & Active Serial Configuration Schemes". Basically it's an AS configuration circuit with additional JTAG header. No switch or similar element is required for it, because JTAG takes precedence over AS, you should however observe the comments about disabling configuration with a blank device. 

 For newer devices, e.g. Cyclone III, the a circuit for the combined scheme is shown in the device handbook.  It should be noted, that the AS flash can be also written through JTAG indirect programming for all Cyclone family FPGAs series, so the AS header isn't strictly required.

[Altera_Forum]

Thanks! Simplicity is always best!

[Altera_Forum]

Hello, Apologies for the delay in reply, but would you be able to point me in the direction of a document on how to "indirect" program the EPC flash via the using the JTAG port? I have searched the forums as well as google and have come up empty...

[Altera_Forum]

1. open File > Convert Programming Files 
2. select .jic (JTAG indirect) as the output type 
3. select appropriate EPCS device 
4. click SOF data, then Add File to add your .sof 
5. click properties to optionally enable compression 
6. click Flash Loader then Add Device to select your target device 
7. click Generate 
8. open Tools > QII Programmer 
9. click Auto Detect 
10. double click in File column of your FPGA device row 
11. select .jic file 
12. click the Program/Configure check box in the new EPCS device listed 
13. click Start 

[Altera_Forum]

Thanks! Your brevity is very much appreciated.. I did find the indirect programming reference document right after I asked the question, but your cliff notes version is much better.. thanks again

[Altera_Forum]

Note that when you have the Convert Programming File window set up how you want it you can save the configuration as a *.COF file. 

 You can then create a *.tcl file to run the conversion, the following uses JIC_conversion.cof and is saved as generate_jic.tcl... >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> set module [lindex $quartus(args) 0]   if [string match "quartus_asm" $module] {  # Include commands here that are run after the assember post_message "Running after assembler" set cmd "quartus_cpf -c JIC_conversion.cof"  # If the command can't be run, return an error. if { [catch {open "|$cmd"} input] } { return -code error $input } } >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>   ..then add a line to your *.qsf so this is automatically run at the end of every compilation.......   set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:generate_jic.tcl"   This has saved me a lot of time in the past (when I've forgotten to do the conversion and wondered why the problem isn't fixed).     Nial.