Signal tap problem

[Altera_Forum]

Hello 

 I have made a design in which I have declared my own datatype. (N is generic) I got the same problem with a fixed value of N in the range.  type data_arr is array (1 to N) of integer;  signal epsilon_1_arr : data_arr;  For epsilon_1_arr in signal tap, mostly all other data in the array except index 1 are red in the "name" column and the values of them are fixed to 0 (integer) even for index 1. The array are filled with values like this:  epsilon_1_arr(2) <= start_epsilon; //constant integer value  Why can't I view the array-data in signal tap?   /Fredrik

[Altera_Forum]

I guess, the array elements aren't synthesized as signals, e.g. because they can't be written or are never read in the design. Signaltap can only access signals, that actually exist in your design.

[Altera_Forum]

I would also think the "shown red" data are "synthesized away" either as there is no code depending on the content (thus these registers would in "hardware" have nothing connected to the output and are therefore optimized by being removed and thus not tappable) or the "names" are synthesized away, i.e. if you assign these values to other signals, sometimes the "assigned to" signals can be tapped... 

 Don't know if that helps any further... Carlhermann

[Altera_Forum]

Thanks for the help! I solved it by removing the arrays and just using individual signals, works fine in Signal tap. 

 /Fredrik

[Altera_Forum]

I know I am digging up an old thread, but I ran into a slightly different problem, but would like to add a solution: 

 I already use the following constructs to have Quartus not synthesize away my debugging signals, this works every time:  attribute noprune : boolean; signal diff_cnt : integer range 0 to 124999999; attribute noprune of diff_cnt : signal is true;  Basically, this will save my signal diff_cnt from being optimized away, even though it may never be actually read anywhere, which normally will cause it to be optimized away as useless logic.  Then I had an array that would never show up in Signal Tap correctly:  Declaration:  type diff_array is array (0 to 7) of std_logic_vector(31 downto 0); signal diffs : diff_array; signal diff_index_cnt : integer range 0 to 7;  Usage:  diff_index_cnt <= diff_index_cnt + 1; diffs(diff_index_cnt) <= std_logic_vector(to_unsigned(diff_cnt,32));  However, once I've added the initializations for instance in case of a reset:   diffs <= (others=> (others=>'0')); diff_index_cnt <= 0;  the array finally showed up in Signal Tap as one would expect.  Hopefully this will help some fellows to debug their stuff without Quartus removing all the debug info or having to connect the debug info to virtual output pins (which will also prohibit Quartus from removing the stuff duing compile).