aocl program: Program failed. Error reading aocx file.

[Altera_Forum]

Hi All, 

 I compiled boardet.cl on server  # aoc --no-interleaving default boardtest.cl -o boardtest.aocx .   when I try to pogram FPGA o board , I get the following error. # aocl program acl0 ./boardtest.aocx# aocl program: Running program from /opt/altera/aocl-rte/board/<...>/linux64/libexec aocl program: Program failed. Error reading aocx

[jomarm10]

Hi,

Is there any progress on this issue?
I am facing the same issue for some aocx files.

This error only arises when attempting to load a kernel on the FPGA that the fitter was not able to create on the first pass when the modifier -high-effort is set.  This is that the fitter had to make several passes all to create the aocx file.

My setup is :

Stratix 10 MX - BSP v19.3

Quartus 20.1

Environment variables set to enable backward compatibility for BSP (script content at the end of the text)

So, the process I follow is:

1- load the environment variables as listed at the end of the text

2 - compile the kernel with command:

        aoc -g -I $INTELFPGAOCLSDKROOT/include/kernel_headers -v -high-effort device/src/k_conv2D.cl -o k_conv2D.aocx 

-fpc -board=s10mx_hbm

Running the previous command produces this output in the terminal:

Warning: -fpc will override all instances of #pragma clang fp contract(fast)
aoc: Environment checks completed successfully.
aoc: Cached files in /var/tmp/aocl/ may be used to reduce compilation time
You are now compiling the full flow!!
aoc: Selected target board s10mx_hbm
aoc: Running OpenCL parser....
aoc: OpenCL parser completed
aoc: Linking Object files....
aoc: Optimizing and doing static analysis of code...
aoc: Linking with IP library ...
aoc: Checking if memory usage is larger than 100%...
aoc: Memory usage is not above 100.
aoc: First stage compilation completed successfully.
aoc: Compiling for FPGA. This process may take several hours to complete. Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets. If the reports indicate performance targets are not being met, code edits may be required. Please refer to the Intel FPGA SDK for OpenCL Best Practices Guide for information on performance tuning applications for FPGAs.
High-effort hardware generation selected, compile time may increase signficantly.
kernel fitting error encountered - retrying aocx compile with attempt: #1
kernel fitting error encountered - retrying aocx compile with attempt: #2
kernel fitting error encountered - retrying aocx compile with attempt: #3
aoc: Hardware generation completed successfully.

After this process, the aocx file is present in the folder, but when I try to load the kernel in the FPGA, it fails displaying the following message

user@host:~$ aocl program acl0 k_conv2D.aocx
aocl program: Running program from /opt/intel_boards/s10mx_ref_original/linux64/libexec
aocl program: Program failed. Error reading aocx file.

This error only happens for the configurations of the kernel that trigger the "high-effort" policy to make the retries due to the fitter errors. 

For smaller kernels (under the same terminal with the same environment ), where during the aocx generation the terminal does not display the retry message, I can successfully program the FPGA with their aocx kernel files.

So, my question is, is there any way I can get more information on the cause of the error

Does anybody know whether it is possible to get the binary file out of the aocx to program the FPGA ? or maybe the tool generated a corrupted aocx file?

Any light on this would be very welcome.

Thanks

------------

Envrionment variables script

-------------------------------------------------------------------------------------

export IQ_VER="20.1"
export IQ_BASE_DIR="/opt/intelFPGA_pro/${IQ_VER}"

export BSP_VER="19.3"
BSP_PATH="/opt/intel_boards/s10mx_ref_original"

export INTELFPGAOCLSDKROOT="$IQ_BASE_DIR/hld"
export QSYS_ROOTDIR="$IQ_BASE_DIR/qsys/bin"
export QUARTUS_ROOTDIR="$IQ_BASE_DIR/quartus"

#setting QUARTUS_ROOTDIR_OVERRIDE for backwards compatibility with stratix bsp $BSP_VER"
export QUARTUS_ROOTDIR_OVERRIDE="/opt/intelFPGA_pro/$BSP_VER/quartus"

#updating PATH
export PATH=$PATH:$QUARTUS_ROOTDIR/bin:$QSYS_ROOTDIR:$INTELFPGAOCLSDKROOT/bin

#setting ModelSim variables and updating path
export MODELSIM_PATH="$IQ_BASE_DIR/modelsim_ae"
export MODELSIM_BIN="$MODELSIM_PATH/bin"

export PATH=$PATH:$MODELSIM_BIN

export AOCL_BOARD_PACKAGE_ROOT="${BSP_PATH}"

#calling init_opencl script"
source $INTELFPGAOCLSDKROOT/init_opencl.sh

#Setting LIBRARY_PATH environment variable
export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu:$LIBRARY_PATH

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