handling with differential signals in quartus II

[Altera_Forum]

Hi at all, 

I have a generel question about handling with differential signals in quartus II.  Is it necessary to create two pins (p and n) in schematic for a differential signal or is it usual to use one pin and define the signal as differential (e.g. as LVDS) in pin planner? In this case the pin planner creates the related negative signal. When I compile my design with one pin quartus reports a warning that quartus automatically generates the negative pin. because of the warning it seems that this approach is not the normal way.  I hope there is someone who can explain the correct handling with differential signals.  best regards  occino

[Altera_Forum]

i don't use differential signals in my RTL (except for transceiver or memory IP that have them already), i just assign a differential I/O standard 

 i can see how the Warning might be a bit alarming. try back annotating the (n) pin assignment, that might suppress the warning. right click the (n) pin in Pin Planner and choose the option regarding back annotating

[Altera_Forum]

The warning is a recent addition. Previously you only had the option of defining the 'p' pin of the differential pair, and the other pin was inferred. 

 You can now specify the n pin. For example, if clkin_100MHz is an LVDS signal with the p pin on A21, and the n pin on A20, you can set the p pin assignment using the signal name clkin_100MHz, and the n pin assignment using the signal name clkin_100MHz(n). You would then apply the LVDS constraint only to clkin_100MHz, not to clkin_100MHz(n).  Cheers, Dave