Set false path in VHDL file instead of .sdc file - Intel Community

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Set false path in VHDL file instead of .sdc file

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Hi everyone,

I was wondering if it is possible to set a "false path" attribute in VHDL instead of doing it in the .sdc file?

I know it was possible with Xilinx, you could add a "TIG" attribute in VHDL directly.

Thanks

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you'll have to tweak it for VHDL:

http://www.alteraforum.com/forum/showthread.php?t=24028

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