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I made the signal with NCO IP. We then testbench the signal. First, I added .sip and .qip files to the project and compiled the following code. But I got an error and I do not know why.
https://www.alteraforum.com/forum/attachment.php?attachmentid=13968&stc=1 https://www.alteraforum.com/forum/attachment.php?attachmentid=13969&stc=1Link Copied
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The device you're targeting doesn't have enough memory resources to implement the IP you're instantiating. Try compiling it for a larger device.
Cheers, Alex- Mark as New
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--- Quote Start --- The device you're targeting doesn't have enough memory resources to implement the IP you're instantiating. Try compiling it for a larger device. Cheers, Alex --- Quote End --- BUT chip of my FPGA device is EP4CE40F23C7. what is the bigger than this. AND IS it Ok to change the device in quartus?
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--- Quote Start --- BUT chip of my FPGA device is EP4CE40F23C7. what is the bigger than this. AND IS it Ok to change the device in quartus? --- Quote End --- If that is your chip, then the IP you have created will not fit into it, and you will either need to modify the IP or buy a new device.
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--- Quote Start --- If that is your chip, then the IP you have created will not fit into it, and you will either need to modify the IP or buy a new device. --- Quote End --- Can i modify NCO IP to usage of RAM?
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--- Quote Start --- Can i modify NCO IP to usage of RAM? --- Quote End --- You certainly can. I believe you have entered excessive figures for lut size (phase resolution). try 2^10 fr phase, 2^10 for amplitude.
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