TimeQuest Constraints

Altera_Forum · ‎03-27-2012

Hello,

I have the following lines of code from a .ucf file that I need to convert for the TimeQuest Timing Analyzer.

net "dff_q_p" offset = in 4 ns before "clk_125_prebuf" high ;

net "controller/mem_data<0>" tnm_net = "mem_data";

net "controller/mem_addr<0>" tnm_net = "mem_addr";

TIMESPEC "TS_DS_address" = FROM "mem_data" TO "mem_addr" 8 ns;

should i use the set_max_delay command?

thanks!

Altera_Forum · ‎03-27-2012

I believe the first one is just an I/O constraint that works the same way as set_input_delay. (I always forget the BEFORE/AFTER difference, although they are opposites).

Are mem_data and mem_addr I/O pins? If so, set_max_delay should work fine. Remember that if you also have any set_input/output_delay constraints on those ports, they will be added into your set_max_delay analysis.

Altera_Forum · ‎04-05-2012

Appears do by Xilinx notation, right?

You can use the SDC Editor to "synthesize" SDC compatible commands.

Another question:

Why is there a 8ns delay between ADR and DAT??

Strange...