Verilog 'include in Quartus

[Altera_Forum]

Hi, 

 I'm trying to use the following header constructs in verilog to be able to use parameterised modules defined by a header file.   Header File cut down example code : (basically just parameters)  `ifndef _HeaderIncluded `define _HeaderIncluded  // Global Parameters parameter pSysClkPeriod = 10, parameter pExampleParam = 5  `endif //_HeaderIncluded   Source File Cut down example : (just the module port declaration part)   module MasterTopLevel  # (`include "Header.v") (  ////  // System Interface  ////  input SysClk,  input SysReset,  It all goes though Modelsim and simulates fine but in synthesis Quartus gives the following error :  Error (10170): Verilog HDL syntax error at MasterTopLevel.v(29) near text ")"; expecting "parameter"  {NOTE : line 29 is the line# (`include "Header.v") }  Its as if the include directive isn't being followed and replacing the text with the text from the header file.  Done a large amount of VHDL designs but Verilog relatively untried with Quartus at least. Is there anything obviously wrong here? Does Quartus support parameterisation like this ?  Any help gratefully received.  **** UPDATE  It seems that this error does not occur on the first file in my project that has this parameterisation, but following files which have the same parameterisation bring up this error ....

[Altera_Forum]

The Verilog specification says in Paragraph 19.5 

  --- Quote Start ---  Only white space or a comment may appear on the same line as the `include compiler directive.  --- Quote End ---   Although apparently supported by Modelsim, the shown include syntax isn't based on specified Verilog behaviour.  In addition, I don't understand why it shouldn't be possible to include full lines of text?

[Altera_Forum]

Even though modelsim supports this, you would be much better off writing your code as 

 module MasterTopLevel # ( `include "Header.v" )  You would get better syntax error messages if there were problems with your code and you included it this way.