Problem Vhdl the process with Reset option

[Altera_Forum]

I have written VHDL code for VGA controller for spartan 3E board. The code simulates and works well without the reset and clk process in the code below. But after inserting the process(reset,clk) the h_count and v_count counters stop counting and are driven to XXXXX undefined in simulation. Where am i going wrong. The code works perfectly without the clk,reset process, I have tested the code on harware also. 

 The code for VGA Controller  ----------------------------------------------------------------------------------  -- Engineer: Shivukumar, Prakash, Shrikant, Dhananjaya Kumara --  -- Create Date: 13:55:45 28/02/2012  -- Design Name: VGA Controller -- Module Name: vga_controller - Behavioral  -- Project Name: VGA Interfacing -- Target Devices: Xilinx Spartan 3E -- Tool versions:  -- Description:   ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL;   entity vga_controller is  port ( clk: inout std_logic;   clk_50 : in std_logic;  hsync,vsync : out std_logic;  video_on : out std_logic;  x_pos,y_pos : out std_logic_vector(9 downto 0);  sw : in std_logic_vector(2 downto 0) := "100";  rgb : out std_logic_vector(2 downto 0)  ); end vga_controller;  architecture Behavioral of vga_controller is signal h_count,v_count : unsigned(9 downto 0) := (others => '0'); begin     freq_dividr : entity work.t_ff port map(clk_50,clk); -- Frequency divider to get 25 MHz clk from 50 MHz clock of Spartan 3E   process(clk,reset) -- if i remove this process everyting works fine. why ????  begin  if reset = '1' then  h_count <= (others => '0');  v_count <= (others => '0');  video_on <= '0';  elsif clk'event and clk = '1' then  h_count <= h_count;  v_count <= v_count;  end if;  end process;   process(clk) -- Process for horizontal counter  begin  if clk'event and clk = '1' then  if h_count = 799 then  h_count <= (others => '0');  else  h_count <= h_count + 1;  end if;  end if;  end process;      process(clk) -- Process for vertical counter  begin  if clk'event and clk = '1' and h_count = 799 then  if v_count = 524 and h_count = 799 then  v_count <= (others => '0');  else  v_count <= v_count + 1;  end if;  end if;  end process;      hsync <= '0' when (h_count >= 656 and h_count <= 751) else -- H_SYNC generation  '1';  vsync <= '0' when (v_count >= 490 and v_count <= 491) else -- V_SYNC generation  '1';  video_on <= '1' when (h_count <= 649 and v_count <= 479) else -- VIDEO_ON Signal  '0';  rgb <= sw when (h_count <= 649 and v_count <= 479) else "000";  x_pos <= std_logic_vector(h_count);  y_pos <= std_logic_vector(v_count);  end Behavioral;

[Altera_Forum]

Your first process says "on every clock, don't change the value of h_count or v_count" so that's what it does. Just ditch that first process and move the reset condition inside the others. 

 Mark.

[Altera_Forum]

@wolforth 

If i change the code as you said it works, But if i replace the first process by this one  process(reset)  begin  if reset = '1' then  h_count <= (others => '0');  v_count <= (others => '0');  video_on <= '0';  end if;  end process;  It doesn't work. Why? I tried to find a book that would clearly address these issues but couldn't find any. Can you suggest any solid book?  Thank you

[Altera_Forum]

Hi, 

 you can not drive h_count/v_count in two different processes. This will result in an undefined value (as you can see in your simulation). You should use something like that : process(clk,reset) begin  if reset = '1' then  h_count <= (others => '0');  elsif (clk'event and clk = '1') then  ..   Regards, HJS

[Altera_Forum]

HJS noticed one of big VHDL coding errors. 

by the way of shivukumar's code, there will be conflicts that the simulator solves with resolving functions in std_logic packages. It is like connecting 2 outputs together !   I may add :  Use STD_uLOGIC and STD_uLOGIC_VECTOR.

[Altera_Forum]

Any book suggestions that address these issues?

[Altera_Forum]

I think Altera coding style book on altera litterature web gives good advices. http://www.altera.com/education/training/courses/ohdl1110?gsa_pos=2&wt.oss_r=1&wt.oss=vhdl and others 

On http://www.doulos.com/   keep in mind that vhdl is a description langage (not a programming langage) For example, in you first post, you tried to connect 2 outputs together. For an hardware designer, it is prohibited except for tri-state, open drain...