How to check clocks using SignalTap II Logic Analyzer?

[Altera_Forum]

Hi all, 

 I am learning how to use Signaltap II logic analyzer using this tutorial:  http://www.altera.com/literature/hb/qts/qts_qii53009.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=design%20debugging%20using%20the%20signaltap%20ii%20logic%20analyzer  Among many advantages of using this analyzer, my first basic concern is how to use the ELA to check/confirm the system clock of a design running in FPGA device? I want to make sure that the clock is fed properly.  PS: Actually, I have checked the clock using the JTAG_debug service with the commands jtag_debug_sample_clock and jtag_debug_sense_clock. But the result seems to be not consistent as sometimes clock is toggled and sometimes not. If someone can help explain how to use these commands to verify clock?  Any comment or suggestion is highly appreciated. Thanks in advance.

[Altera_Forum]

To see the clock in the Signal-tap A higher sampling input is needed to sample may be (3 to 4 times more frequency than the clock you want to see)

[Altera_Forum]

jtag_debug_sample_clock does just that, it reads the clock signal at the time you ask for it, so sometimes you'll get a 0 and sometimes you'll get a 1. 

jtag_debug_sense_clock returns 1 if the clock toggled since the last time you called jtag_debug_sense_clock and 0 otherwise. You may get a 0 after the first call (I never did, but you never know) but after that you should only get 1's. If you get 0's after then you probably have a problem. In SignalTap if the clock you selected a a sampling clock isn't toggling, SignalTap will tell you so. (I don't remember the exact message, but it's different than 'waiting for trigger')

[Altera_Forum]

--- Quote Start ---  To see the clock in the Signal-tap A higher sampling input is needed to sample may be (3 to 4 times more frequency than the clock you want to see)  --- Quote End ---    Thanks kalyansrinivasm for your advice. How do you come to know that the sampling clock must be 3 to 4 times higher in freq, if it is stated somewhere or just your experience?

[Altera_Forum]

--- Quote Start ---  jtag_debug_sample_clock does just that, it reads the clock signal at the time you ask for it, so sometimes you'll get a 0 and sometimes you'll get a 1. jtag_debug_sense_clock returns 1 if the clock toggled since the last time you called jtag_debug_sense_clock and 0 otherwise. You may get a 0 after the first call (I never did, but you never know) but after that you should only get 1's. If you get 0's after then you probably have a problem. In SignalTap if the clock you selected a a sampling clock isn't toggling, SignalTap will tell you so. (I don't remember the exact message, but it's different than 'waiting for trigger')  --- Quote End ---    Thanks Daixiwen very much. I wonder if we can set the sampling time for reading clock? and what is the default time interval if I just invoke two consecutive sample_clock commands, is it in ns or ms?  is it possible to calculate the clock frequency through the results of jtag_debug service?  Thanks.

[Altera_Forum]

--- Quote Start ---   is it possible to calculate the clock frequency through the results of jtag_debug service?   --- Quote End ---    Here's how I test clocks;  1) Create a basic design where an LED blinks at about 1 Hz. If the board has more than one clock, then assign an LED (or two) to each clock.  2) Create a JTAG-to-Avalon-MM design with a clock-counting register block. The clock counter component contains several counters each clocked by an external source. The counters each have an enable input. The enable input comes from an Avalon control register, and is synchronized to each of the respective clock domains. You pulse the enable signal using JTAG commands, and then read out the counter values.  The counter value for the Avalon clock is your reference clock count, eg., lets say I used a 50MHz on-board oscillator for the Avalon clock, the assumption is that that oscillator is exactly 50MHz.  Read the counts in the other counters, and scale them from count to MHz using the reference count.  This is very handy for checking that your PLLs and transceiver clocks are operating at the right frequencies.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  How do you come to know that the sampling clock must be 3 to 4 times higher in freq, if it is stated somewhere or just your experience  --- Quote End ---  From Nyquist principle any signal should be sampled more than twice its operating frequency  So for better results sample it using 3 to 4 times higher frequency clock.

[Altera_Forum]

--- Quote Start ---  Here's how I test clocks;  1) Create a basic design where an LED blinks at about 1 Hz. If the board has more than one clock, then assign an LED (or two) to each clock.  2) Create a JTAG-to-Avalon-MM design with a clock-counting register block. The clock counter component contains several counters each clocked by an external source. The counters each have an enable input. The enable input comes from an Avalon control register, and is synchronized to each of the respective clock domains. You pulse the enable signal using JTAG commands, and then read out the counter values.  The counter value for the Avalon clock is your reference clock count, eg., lets say I used a 50MHz on-board oscillator for the Avalon clock, the assumption is that that oscillator is exactly 50MHz.  Read the counts in the other counters, and scale them from count to MHz using the reference count.  This is very handy for checking that your PLLs and transceiver clocks are operating at the right frequencies.  Cheers, Dave  --- Quote End ---    Thanks Dave. I will try this soon.   By now, I am playing with the SignalTap Analyzer to test clocks by relative comparison. Again, my purpose is to have a synchronous clock for dual-board designs. So, I assign clock like this. The design on the board#1(with the SMA clock output) has input clock assigned to an FPGA pin. This clock is also assigned to the output clock. The design on the board#2 (with the SMA clock input) uses the SMA input clock as the reference.  And something strange happened I don't understand. I use Sinaltap to capture the input clock and output clock in design#1, they are identical. In the board#2, for comparison purpose, I tap the external input clock (coming from board#1 via SMA connectors). and a local clock signal with exactly same frequency (100MHz). But the external input clock is strange, not stable, having too many bit 1s and only 1 bit 0 in a period, while the expected clock should have a duty cycle of 50% (like 1111000011110000).   If anyone has experienced something similar, please share your solution? Or if the quality of SMA cables can be the reason?   Thank you.

[Altera_Forum]

--- Quote Start ---   So, I assign clock like this. The design on the board#1(with the SMA clock output) has input clock assigned to an FPGA pin. This clock is also assigned to the output clock. The design on the board#2 (with the SMA clock input) uses the SMA input clock as the reference.   --- Quote End ---    Ok, good.    --- Quote Start ---   And something strange happened I don't understand. I use Sinaltap to capture the input clock and output clock in design#1, they are identical.    --- Quote End ---   What is your SignalTap II clock reference on Board#1?    --- Quote Start ---   In the board#2, for comparison purpose, I tap the external input clock (coming from board#1 via SMA connectors). and a local clock signal with exactly same frequency (100MHz).   --- Quote End ---    Its not phase locked though. If you are SignalTapping a 100MHz incoming clock with a 100MHz local clock, then you'll get weird sample captures, since the two clocks will be sliding relative to each other.  Rather than doing the test this way, use the 100MHz input as either the input to a clock-divider or to a PLL. Generate say a 10MHz clock. Then SignalTap that 10MHz signal using the 100MHz clock on Board#2.  Using counters is much more reliable, since the logic operates in its own respective clock domain.  Cheers, Dave

[Altera_Forum]

Thanks Dave, 

   --- Quote Start ---  What is your SignalTap II clock reference on Board#1?   --- Quote End ---   I also use 100MHz clock as clock reference in board#1. In both sides, I use another clock for sampling in signaltap II is 576 MHz.    --- Quote Start ---  Its not phase locked though. If you are SignalTapping a 100MHz incoming clock with a 100MHz local clock, then you'll get weird sample captures, since the two clocks will be sliding relative to each other  --- Quote End ---  . I did this because first, I want to see if the period and the shape of the two clocks look similar in terms of visualization (normal eyes). And the fact that they looked totally different makes me believe that there exist some problem. And I don't know where it can come from. Do you have an idea?    --- Quote Start ---  Rather than doing the test this way, use the 100MHz input as either the input to a clock-divider or to a PLL. Generate say a 10MHz clock. Then SignalTap that 10MHz signal using the 100MHz clock on Board#2.  Using counters is much more reliable, since the logic operates in its own respective clock domain.  --- Quote End ---    Ok, I got this and will implement this.  Thank you.

[Altera_Forum]

--- Quote Start ---   I use another clock for sampling in signaltap II is 576 MHz.   --- Quote End ---    Ok, so you should see something that looks like a square wave then.    --- Quote Start ---   I did this because first, I want to see if the period and the shape of the two clocks look similar in terms of visualization (normal eyes).   --- Quote End ---   You won't see that with SignalTap. You need a scope for that sort of visualization.    --- Quote Start ---   And the fact that they looked totally different makes me believe that there exist some problem. And I don't know where it can come from. Do you have an idea?   --- Quote End ---    Look at the clock output with an oscilloscope. Look at the schematic.  Is the SMA output clock direct from an FPGA pin or does it have a series termination resistor?  Is the SMA input clock direct to an FPGA pin or does it have a buffer between the SMA and the FPGA or does it have a termination resistor? Is it AC coupled or DC coupled? Have you terminated the transmission line correctly, eg., enable a parallel termination if an external one does not exist?  That's a few things for you to think about.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Ok, so you should see something that looks like a square wave then.  --- Quote End ---   Yes, I see square wave for any any signal except the external input clock.    --- Quote Start ---  You won't see that with SignalTap. You need a scope for that sort of visualization.  --- Quote End ---    I have tried this with Oscilloscope today, and I found that there was no signal coming out from SMA connectors (only noise). I checked again the board schematic and reference manual. I am not so sure but it looks like I can only drive the reference clocks (dedicated for XCVR channels) out of the board, but not the clock from core.  One point I am still confused. I am trying to have a synchronous global system clock that is used for managing and reconfigurating local MAC, PHY, traffic controller components basically. Is this necessary to have this synced when building the dual-board communication? Otherwise, the transceiver reference clock, 156.25 MHz, is used for both Ethernet TX and RX to work. My wonder is should I just make this reference clock synced or I need also to have the system clock synced? Can you help to give an advice?  Thanks again.

[Altera_Forum]

--- Quote Start ---   I have tried this with Oscilloscope today, and I found that there was no signal coming out from SMA connectors (only noise). I checked again the board schematic and reference manual. I am not so sure but it looks like I can only drive the reference clocks (dedicated for XCVR channels) out of the board, but not the clock from core.   --- Quote End ---    If an SMA goes to a REFCLK, that is an input path, not an output.  Look on page 11 of the schematic, there are two SMA connectors, IO_CLKOUT1 and IO_CLKOUT2. Page 25 shows where they come from; PLLT1CKO0p/n.   Those pins sound like they are a PLL output ... is that what you are using?  What about page 9, J18, it comes from U21 (ICS557-03). That should be a clock signal too. I'd recommend using this one, since it will not accumulate PLL jitter from the FPGA.     --- Quote Start ---   One point I am still confused. I am trying to have a synchronous global system clock that is used for managing and reconfigurating local MAC, PHY, traffic controller components basically. Is this necessary to have this synced when building the dual-board communication? Otherwise, the transceiver reference clock, 156.25 MHz, is used for both Ethernet TX and RX to work. My wonder is should I just make this reference clock synced or I need also to have the system clock synced? Can you help to give an advice?   --- Quote End ---    Its up to how you want to deploy your system;  1) Synchronous clocks   Can be used when you are using the transceivers for custom applications, where you do not have the option to 'bit-slip' to accommodate differences in frequencies between oscillators on different boards.  2) Asynchronous clocks (of the same frequency)   This is what most networks use. The clocks on the boards are nominally the same frequency, but they are not exactly. The protocol used over the wire has some 'slack' built in, and the transmit or receive sides have FIFOs for matching data rates. The protocols involve bit-sequences that can be stuffed into the transceiver link, or deleted, as needed to match overall data rates.  (1) is simpler to deal with when you are trying to figure stuff out.  Cheers, Dave

[Altera_Forum]

Thanks a lot for your time and very detailed support. 

   --- Quote Start ---  Look on page 11 of the schematic, there are two SMA connectors, IO_CLKOUT1 and IO_CLKOUT2. Page 25 shows where they come from; PLLT1CKO0p/n.   Those pins sound like they are a PLL output ... is that what you are using?  --- Quote End ---    Exactly I am using these pins (J16, J17). Yes, the IO_CLKOUT1/2 come from FPGA pin (M20,L20). So I tried to assign a clock output signal to these pins. What I did is as follows:  1. At transmitter side:  input S4GT_CLK1; //assign S4GT_CLK1 to pin (K34,J34), generated by U21, a 25-MHz oscillator //and spread spectrum clock buffer circuitry, freq is set by rotating DIP Switch //Pin-Out SW2  output IO_CLKOUT1;  assign IO_CLKOUT1 = S4GT_CLK1; //assign IO_CLKOUT1 to pin (M20,L20)  2. Connect SMA cables from (J16->J14), (J17->J15)  3. At receiver side:  input S4GT_EXT_CLK5; //assign S4GT_EXT_CLK5 to pin (AV22, AW22)   input LOCAL_S4GT_CLK1; //assign LOCAL_S4GT_CLK1 to pin (K34,J34)  4. Check S4GT_EXT_CLK5, LOCAL_S4GT_CLK1 with SigntalTap and Oscilloscope And S4GT_EXT_CLK5 is just noise in Scope and looks strange in SignalTap.    --- Quote Start ---  What about page 9, J18, it comes from U21 (ICS557-03). That should be a clock signal too. I'd recommend using this one, since it will not accumulate PLL jitter from the FPGA.  --- Quote End ---    J18 is a SMA output of the S4GT_CLK1 (U21, freq is set by rotating SW2). Whenever the board is on, we have the clock output from J18. Also I have checked this clock signal and it is nice in both Scope and SignalTap.  But in case we use this, my wonder is that, the S4GT_CLK1 is a differential clock source at the TX. But when we drive it out from J18, we have only one cable. Given that RX also need a pair of clock signal from SMA pin (J16,J17), how can we feed the two connectors with only J18? Do I need something to make a clock to differential clock or I just use either connector of the pairs?   Thanks again.

[Altera_Forum]

--- Quote Start ---   1. At transmitter side:  input S4GT_CLK1; //assign S4GT_CLK1 to pin (K34,J34), generated by U21, a 25-MHz oscillator //and spread spectrum clock buffer circuitry, freq is set by rotating DIP Switch //Pin-Out SW2  output IO_CLKOUT1;  assign IO_CLKOUT1 = S4GT_CLK1; //assign IO_CLKOUT1 to pin (M20,L20)   --- Quote End ---  I don't see anything wrong with your connections.  What was the I/O standard you assigned to IO_CLKOUT1?    --- Quote Start ---   J18 is a SMA output of the S4GT_CLK1 (U21, freq is set by rotating SW2). Whenever the board is on, we have the clock output from J18. Also I have checked this clock signal and it is nice in both Scope and SignalTap.   --- Quote End ---  So use this one then.    --- Quote Start ---   But in case we use this, my wonder is that, the S4GT_CLK1 is a differential clock source at the TX. But when we drive it out from J18, we have only one cable. Given that RX also need a pair of clock signal from SMA pin (J16,J17), how can we feed the two connectors with only J18? Do I need something to make a clock to differential clock or I just use either connector of the pairs?    --- Quote End ---  You just need to determine whether or not you violate any input voltage specifications.  For example, note how page 11 has 50-ohm terminations to ground for S4GT_EXT_CLK5 and they lead directly to the FPGA clock pins. You can probably configure one of those signals as a single-ended clock, and then directly connect the single-ended output on J18 to the SMA J14.  Just make sure that the voltage swing of the J18 output does not violate the voltage swing on the FPGA input. Check with a scope for reflections. If things look ugly, put a 50-ohm source termination on J18 before you attach the SMA cable. It'll drop the voltage by half.  Because the S4GT_EXT_CLK5 will be routed differentially, there will be some switching noise coupled onto the N of the differential pair. But its terminated in 50-ohms to ground, and you're not using the N input at the FPGA, so that'll be fine.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  What was the I/O standard you assigned to IO_CLKOUT1?  --- Quote End ---    The I/O standard is 2.5V.    --- Quote Start ---  You can probably configure one of those signals as a single-ended clock, and then directly connect the single-ended output on J18 to the SMA J14.  --- Quote End ---    How can I do this?    --- Quote Start ---  Check with a scope for reflections. If things look ugly, put a 50-ohm source termination on J18 before you attach the SMA cable. It'll drop the voltage by half.   --- Quote End ---   How to put the source termination on the J18? Sorry, I am not an electronic guy so this basic stuff is also new to me.  Well, I just think of driving out the reference clock from one of the three generators dedicated to XCVR blocks (100, 644.25, 706.53Mhz). These are differential clocks and we can drive those to J16, J17. Especially, the clock 100Mhz can be used for system clock instead of using S4GT_CLK1 (U21). How do you think about this?  Thanks.

[Altera_Forum]

--- Quote Start ---  The I/O standard is 2.5V.   --- Quote End ---  That is not a differential standard. If you were assigning a single-ended standard to the output clock P+N signal and using them as a differential signal, then the difference would be nothing. However, you mentioned you looked with a scope, so you would have noticed that :)  To define the input clock as single-ended, just assign it as an input with 2.5V LVCMOS logic level, or 3.3V logic level, whatever is appropriate for that I/O bank (check the schematic to ensure you use the right setting).     --- Quote Start ---   How to put the source termination on the J18? Sorry, I am not an electronic guy so this basic stuff is also new to me.   --- Quote End ---  Put a 50-ohm resistor in series with the cable. Either chop up a cable, or buy a series termination. Minicircuits might have something (though you might only find end-terminations). Ignore this for now.    --- Quote Start ---   Well, I just think of driving out the reference clock from one of the three generators dedicated to XCVR blocks (100, 644.25, 706.53Mhz). These are differential clocks and we can drive those to J16, J17. Especially, the clock 100Mhz can be used for system clock instead of using S4GT_CLK1 (U21). How do you think about this?   --- Quote End ---  Any time you drive a clock out of the FPGA, you will increase the jitter. However, sure, any of these schemes should work. In fact all of them should. But first, you need to get just one to work :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  To define the input clock as single-ended, just assign it as an input with 2.5V LVCMOS logic level, or 3.3V logic level, whatever is appropriate for that I/O bank (check the schematic to ensure you use the right setting).  --- Quote End ---    I can only fine 3.3V LVCMOS but not 2.5V LVCMOS in the list. Also, besides 3.3V LVCMOS, level 3.3V LVTTL is usable for single-ended signal?  Thanks

[Altera_Forum]

--- Quote Start ---   Just make sure that the voltage swing of the J18 output does not violate the voltage swing on the FPGA input.  --- Quote End ---   In case we violate the limited voltage, if Quartus recognizes and stop with an error? and what is the worst case if we misassign the I/O standard for pins?

[Altera_Forum]

--- Quote Start ---  I can only fine 3.3V LVCMOS but not 2.5V LVCMOS in the list. Also, besides 3.3V LVCMOS, level 3.3V LVTTL is usable for single-ended signal?   --- Quote End ---  Before you care what Quartus allows you to do, you should first check what has physically been implemented.  p11 S4GT_EXT_CLK5P/N J14/15 route to p23 AV22/AW22 which are clock inputs on Bank 3C. Page 27 shows the power. Bank 3C is connected to 2.5V.  With that knowledge, the only valid Quartus settings are LVDS or 2.5V LVCMOS.  In the case of using this pin for a single-ended input, it should allow you to select 2.5V LVCMOS.  Your comments are too vague; what list (where in Quartus) and for what pins?  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  In case we violate the limited voltage, if Quartus recognizes and stop with an error? and what is the worst case if we misassign the I/O standard for pins?  --- Quote End ---  If you violate the input voltage, you will damage the input clock pin on your expensive board, and it (that pin, and perhaps others) will never work again.  Check the signals with an oscilloscope before you plug them in!!  Quartus will not protect you.  Cheers, Dave