Downloading ELF Process failed of Project

[Altera_Forum]

Good night everybody , I have problem of QuartusII 10.1sp1 . 

 My user chip is CycloneII EP2C35FC8 , when my sopc builder use  Pll、SDRAM、FLASH、MCU、JTAG , I can run as hardware of holld_world .  (Eclipse - Application and BSP from Template)   But , when I return sopc builder and add EnthModule、DMA(*2-RX、TX)、  onchip momery(4096bytes)、timer . And Auto-Assign Base Addres、IRQS.  Compilation after , I run as web_server_socket(rgmii)   (Eclipse - Application and BSP from Template) ,   but message tell me , downloading elf process failed .   So , I try again run as holld_world , but message still tell me  downloading elf process failed .   Would like to ask anyone encountered a similar problem : ( ?

[Altera_Forum]

You should have another error message before this one that tells you why the download failed. 

Do you have a system id component in your sopc project? If not then add it first. It will ensure that you are using the correct configuration. IF you don't have a license for the Nios CPU you are using, then there is an opencore evaluation window that will open after you configure the FPGA. Don't close this window or the CPU will stop working. Check also that the design is properly constrained and meet all timing requirements.

[Altera_Forum]

Dear Daixiwen 

 Thanks your answer , I found my sopc builder ,   haven't System id component , so I add this component ,  moreover move the top and Auto-Assign Base Addres、IRQS .   when I finish compilation , I programmer project for my board .  (still keep open the programmer window)  Then I use Eclipse and creat Application and BSP from Template .  When I run as web_server_socket(rgmii) , the message still tell me  downloading elf process failed   but appear the message befor , have other message .  The message tell me   assertion "m_state==state_debug" failed : file   "nios2oci.cpp",line 158  using cable "usb-blaster [usb-0]", device 1 , instance 0x00  pausing target processor : not responding .  resetting and trying again : /cygdrive/c/altera/10.1sp1  /nios2eds/bin/nios2-download : line 601: 2380 hangup.

[Altera_Forum]

--- Quote Start ---  pausing target processor : not responding .  --- Quote End ---  This usually means one of the following:[list][*]you are in opencore evaluation mode and you closed the window after programming the FPGA[*]bad clock and/or reset signals[*]design not meeting timing requirements[/list]

[Altera_Forum]

Dear Daixiwen 

 I reference your support and read some datasheet .  I found , my problem maybe come from my memory config .  In my project , when I just use (sopc builder)  pll、nios、sdram、flash、jtag haven't problem .  But , when I add Enth Module、DMA、on-chip(ram or rom)  the niosII will tell me downloading elf process failed of project  Near, I read datasheet of page 6  http://www.altera.com/literature/manual/mnl_avalon_spec.pdf  I think ,maybe I need use FIFO Buffer(on-chip) replace on-chip(ram or rom)  but I still tree , because i first use this fifo buffer(on-chip)

[Altera_Forum]

Is your design properly constrain and does it meet all timing requirements? When a design stop workings after adding some components usually indicates a timing problem. Adding some components should not cause the processor not to respond on the JTAG interface.

[Altera_Forum]

Dear Daixiwen 

 sorry Daixiwen , I don't know your mean ...  My timing requirements problem of your mean ?  but my pll only fore clk clk_0(exteral 50MHZ) 、system_clk(100MHZ) 、   sdram_clk(100MHZ -65deg) 、 enth_clk(25MHZ).   At my sopc builder , only pll use clk_0 , other every use system_clk.   To Blcok Diagram/Schematic File , sdram_clk for sdram clk of pin  Enth_clk for Enth clk of pin , I still don't know my problem from where...

[Altera_Forum]

You must create an sdc file that lists at least all your external clocks. Then when you compile your design, look for any critical warning saying the timing requirements haven't been met. Have also a look in Timequest for the clock report and check that all your clocks have been detected correctly and are at the right frequency.

[Altera_Forum]

Dear Daixiwen 

 I near found this datasheet ↓  http://www.altera.com/literature/manual/mnl_qts_quick_start.pdf  so...your mean is I need set my SDRAM、Flash、On-chip(ram)  of the timing ?

[Altera_Forum]

Yes you have to define in .sdc files your clocks and timing to all fast I/O pins (memories and Ethernet). If you use a development kit you probably have some example designs with ready made .sdc files.

[Altera_Forum]

Dear Daixiwen 

 So , I need read data(CyclonII、Sdram、Flash、Enth Chip...)  and set Timing parameter of your mean ?  And new question , I thinking maybe my problem ,  come from my on-chip(Enth use) timing set ... because   when I remove on-chip , my NiosII haven't problme.  but , when I add Enth Module 、 DMA 、on-chip ...   and my friend tell me , maybe my problem come from the on-chip Timing.  But at Sopc builder , I not found about set Timing parameter of on-chip...

[Altera_Forum]

Yes you need to define your timing requirements. 

For the on-chip memory the only thing you need to define is your clock input frequency and use the derive_pll_clocks command. Timequest will determine all the internal timing from this. For the SDRAM and Flash you need to define the I/O timing.

[Altera_Forum]

Dear Daixiwen 

 so I need return "SOPC Builder"  and set pll of three output :   system_clk(100Mhz)   sdram_clk(100Mhz -65deg)  onchip_clk(100Mhz -130deg) <-- for on-chip(Enth &#9472; DMA use) clk   your mean is this ?  And I still don't understand your mean of defin the i/o timing ...  can you explanation this mean of defin : ) ?

[Altera_Forum]

No, both your clocks and IO timing must be defined in Timequest. Have a look at this user guide (http://www.alterawiki.com/wiki/timequest_user_guide). 

Why are you using a 130 degres phase on the onchip clock? This will create unnecessary timing constraints on the design. Just use the same clock for your system and the on chip ram.

[Altera_Forum]

Dear Daixiwen 

 The 130 degrees set is myself speculate and try use...  M...the User Guide I will read , if I have new found or progress  I will immediately return : )

[Altera_Forum]

Dear Daixiwen 

 I do it of near , because I found   At assignments of setting , in the Timequest Timing Analyzer .  Need add "project_name.sdc" file , the file include Enth_Rx_Clk   and clk50 setting .  But I have new questin ....when I download success ,   The NiosII bsp tell me :  InterNiche Portable TCP/IP , V3.1  Copyright 1996-2008 by InterNiche Technologies. All right reserved. prep_tse_mac 0 your Enthnet Mac address is 00:07:ed:ff:e2:d7 prepped 1 interface , initializing ...  [tse_mac_init] INFO : TSE MAC 0 found at address 0x05002000 error : mac group[0] - no phy connected! error : no phy connected! speed = 100 , duplex = full ok , x=0 , CMD_CONFIG=0x00000000  MAC post-initialization : CMD_CONFIG=0x04000203 [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created mctest init called IP addres of et1 : 0.0.0.0 Created "Inet main" task (Prio : 2) Created "clock tick" task (Prio : 3)   I think ... It is my hardware problem ?  But when I connected to Internet cable  My Internet chip of indicate led is normal...  (ENET_LED_LINK100&#12289;ENET_LED_DUPLEX&#12289;ENET_LED_RX)

[Altera_Forum]

The no PHY connected message means that something is wrong with the MDIO signals - either the clock or the data. Check that you connected them correctly, especially the bidirectionnal data signal, as you have 3 signals to/from the TSE that you need to combine in a single tristate buffer. 

It should still work, as long as the Ethernet connection is using the same speed the TSE is configured to. Without the MDIO communication the TSE has no way of finding out what speed the PHY negotiated on the link.

[Altera_Forum]

Dear Daixiwen 

 I check the Enet_rx_clk_pll component , it is one input three output ,  one input :   ENET0_RX_CLK - 125MHZ from Internet Chip  three output (All 125MHZ) :  enet_rx_clk_270 0° deg to Nios Process input "rx_clk_to_the_tse_mac"  enet_tx_clk_mac 90° deg to Nios Process input "tx_clk_to_the_tse_mac"  enet_tx_clk_phy 180° deg to ddr_o component input "outlock"  (ddr_o is ALTDDIO_OUT , three input , one output of link ENET0_GTX_CLK)  --------------------------------------------------------------- And about ENET0_MDIO config (Verilog file) : assign NET0_mdio_in = ENET0_MDIO; assign ENET0_MDIO = NET0_mdio_oen ? 1'bz : NET0_mdio_out;  NET0_mdio_in : link to Nios process intput mdio_in_to_the_tse_mac NET0_mdio_oen : from Nios Process output mdio_oen_from_the_tse_mac NET0_mdio_out : from Nios Process output mdio_out_from_the_tse_mac ---------------------------------------------------------------  and Nios II Windows have new message   info : phy[0.0] - checking link... info : phy[0.0] - link established warning : phy[0.0] - phy not found in phy profile info : phy[0.0] - speed = 100 , duplex = full  ok , x=0 , cmd_config=0x00000000

[Altera_Forum]

Why are you using those phase shifts on the clock? Just use the same one everywhere. 

What PHY chip do you have? Is it one that is included in the TSE driver?

[Altera_Forum]

Dear Daixiwen 

 About phase shifts on the clock , I reference the de2_115_web_server  of QuartusII config , so I use the enet_rx_clk_pll component.  And my Internet chip is use 88e1111 , and my QuartusII Core is copy   example of web_server_de2_115 , but my core is use CyclonII . at my  hardware indicate led have rx&#12289;duplex&#12289;link1000 .  But link1000 should not be bright...it is abnormal...  should be bright is link100...  (Refer DE2-115 Board , it bright RX&#12289;DUPLEX&#12289;LINk100&#12289;TX(have cable))    TSE driver ? your mean is QuartusII on the setting &#8594; files and add altera   Built-in ip code ? I have do of add that .  (altera &#8594; triple_speed_ethernet &#8594; lib &#8594; ip code)  I think...maybe problem is from my QuartusII Project...or hardware problem  just I think ... and I will keep try : )

[Altera_Forum]

I'm not familliar with the de2-115 kit examples. I've used the Cyclone III developper board, which uses only one clock for the Ethernet connection and it works fine. 

By driver I meant the C driver. The PHY chips drivers are in altera\xxx\ip\altera\triple_speed_ethernet\lib\sopc_builder\altera_triple_speed_ethernet\HAL\src\altera_avalon_tse.c The 88e1111 is a supported PHY chip so you shouldn't see the text "PHY not found in PHY profile". This means you still have a problem with the MDIO communication. Maybe using a scope or Signaltap on the clock and data lines will help you find out what's wrong. It looks like the PHY chip negotiated a 1Gb/s but the driver doesn't now that (as it can't communicate with the PHY) and switch by default to a 100Mb/s speed.