how to understand some note in an477

Altera_Forum · ‎05-02-2012

Hi,

I have some confuse about how to interface a IO referenced by vccio1.8V with a external 3.3V driver.

Quoted from the note#2 of table 1 in an477, “Other I/O standards do not require attention on the maximum input voltage, such as 1.8/1.5/1.2-V LVTTL/LVCMOS, 3.0-V PCI/PCI-X,

voltage-referenced, and differential I/O standards”.

What does it exactly mean? I don't think it mean that I can directly connect the 3.3v driver with the IO powered by vccio1.8V.

Would somebody give me a hint? Thx a lot~~

Altera_Forum · ‎05-04-2012

Can somebody help me??

Altera_Forum · ‎05-04-2012

I guess you are referring to AN447?

The document's main concern is keeping safe input voltages for FPGAs. Driving a FPGA by 3.3V logic is a critical case from it's viewpoint. Using correct source side serial termination there's should be no problem. Previous FPGA families had "Multi-IO" voltage tables saying 3.3V can drive 1.5 to 3.3V CMOS on input.

The input overdriving aspect involves a rather asymmetrical threshold and a certain delay asymmetry. You should also care for a reliable low level. If delay symmetry is an objective, you can think about using voltage dividers as level translaters.