Fatal: (vsim-4) when trying to use SDRAM Controller Generic Memory Model

[Altera_Forum]

I'm trying to simulate a Qsys system with a Nios II processor running code from an external SDRAM, with Modelsim ASE. In order to get a simple RTL simulation, I would like to use the Altera Generic Memory Model, as suggested in Embedded Peripherals IP user guide (p.2-8). 

 When I try to run my hello world application, Modelsim ASE crashes with a "Memory Allocation Failure" error message, code vsim-4. This error disappears when I deselect the "Include a functional memory model in the system testbench" checkbox while istantiating the SDRAM controller core (although in this case I obviously can't run my code).  Any suggestion to get the things working? Thank you in advance for any help you can give.  Regards, Lorenzo

[Altera_Forum]

Till now, I could see that the problem is in the file my_qsys_system_tb_main_memory_my_partner.vhd (where my_qsys_system is the name of my Qsys system and main_memory is the name of the SDRAM controller istance in it). Modelsim ASE goes out of memory when trying to load this VHDL, which seems to serve as the initializer for the SDRAM functional model. 

 First of all, the name of the initialization file (.dat) was not correct so I corrected it with the memory file generated by Nios II SBT. Anyway, Modelsim ASE still fails and I can't find why.  Still working on it, any help would be greatly appreciated!  Regards, Lorenzo

[Altera_Forum]

The inizialization file was set correctly from the beginning, although I can't understand how. 

 Anyway, I have the feeling that Altera SDRAM functional model isn't good at all: the problem with Modelsim is that this VHDL istantiates a big mem_array (array of std_logic_vectors) as a signal instead of as a variable, so causing Modelsim to go out of memory (I read somewhere on the web that mem_array should be instantiated as a variable to avoid this problem).  Again, can anyone from Altera give me any kind of suggestion?  Regards, Lorenzo

[Altera_Forum]

I'm attaching an example design that generates the error as a reference. 

 Regards, Lorenzo